TC9WMA1FK
2001-10-16
1
TOSHIBA CMOS Digital Integrated Circuits Silicon Monolithic
TC9WMA1FK
1,024-Bit (128 8 Bit) Serial E
2
PROM
The TC9WMA1FK is electrically erasable/programmable
nonvolatile memory (E
2
PROM).
Features
Serial data input/output
Programmable in units of one word and collectively erasable
in one operation
Automatically set programming time (built-in timer)
Programming time: 10 ms (max) (V
CC
= 3.0 to 3.6 V)
13 ms (max) (V
CC
= 2.7 to 3.6 V)
Overwriting enabled or disabled by software
Single power supply and low power consumption
Operating power supply voltage (2.7 to 3.6 V)
Wide operating temperature range (-40 to 85C)
Product Marking
Pin Assignment
(top view)
Weight: 0.01 g (typ.)
Type name
US8
8
DI DO
7
6
5
1
2
3
4
GND
NC
V
CC
RST
CLK
CS
TC9WMA1FK
2001-10-16
2
Block Diagram
Pin Function
Pin Name
Input/Output
Function
CS
Input
Chip select
A low on
CS
selects the chip. Always return
CS
high temporarily before
executing instructions.
CLK
Input
Clock input
The data on DI is latched by a rising edge of
CLK
. Data is output to DO by a falling
edge of
CLK
.
CLK
is effective when
CS
is low.
DI Input
Serial data input
This pin is used to enter addresses, commands, and data into the chip.
DO Output
Serial data output
This pin outputs data from the chip.
RST
Input
Reset input
A low on this input resets the chip.
NC
No connection (not connected internally)
V
CC
2.7
V~3.6
V
GND
Power supply
0 V (GND)
Control
circuit
Address
decoder
Power supply
(booster circuit)
Memory cell
Data register
Timing
generator
Address
register
Chip select
Input/Output
circuit
Clock input
Data Input DI
Data Output DO
V
CC
Power supply
Reset input
GND Ground
Command
register
RST
CLK
CS
TC9WMA1FK
2001-10-16
3
Functional Description
1. Types of Instructions
Command
Operation Address
C0 C1 C2 C3
Data
Read A0~A6,
0
1
0
0
0
0
0
0
0
Program
A0~A6,
0
0
1
1
0
0
0
0
0
D0~D7
All erase
********
0
0
1
1
0
0
0
0
Busy monitor
********
1
0
1
1
0
0
0
0
Overwrite enable
********
1
0
0
1
0
0
0
0
Overwrite disable
********
1
1
0
1
0
0
0
0
*
: Don't care
2. Operation Method
Be sure to return CS and CLK high temporarily before entering instructions.
After CS is asserted low, CLK becomes effective, acting as a serial transfer synchronizing signal. The
data on DI is latched by a rising edge of CLK , while data is output to DO by a falling edge of CLK .
Instructions can only be executed when the chip is not being programmed or collectively erased (i.e., when
the ready/busy status signal is high). However, the Busy Monitor instruction can be entered at any time.
Only the commands listed in the above table can be used. Do not use any other command.
(1) Read
When the Read instruction is entered, memory data at the specified address is read out and is
serially output from the DO pin.
(2) Program
When the Program instruction is entered, overwrite operation automatically starts internally in the
chip, and memory data at the specified address is overwritten with the input data. After the
instruction is entered, CS can be returned high even while overwrite operation is in progress
internally.
(3) All
Erase
When the All Erase instruction is entered, erase operation automatically starts internally in the
chip, and memory data at all addresses are erased. After the instruction is entered, CS can be
returned high even while erase operation is in progress internally. Execution of this command clears
the memory data to 0.
(4) Busy
Monitor
When the Busy Monitor instruction is entered, a ready/busy status signal is output from the DO pin.
This output signal is low while the chip is being programmed or collectively erased, and is high after
programming or collective erase operation is completed.
The ready/busy status signal is output continuously until CS is returned high.
(5) Overwrite
Enable/Disable
When the Overwrite Enable instruction is entered, the chip is placed in overwrite enable mode,
where the Program and All Erase instructions are enabled. When the Overwrite Disable instruction is
entered, the chip is placed in overwrite disable mode, where the Program and All Erase instructions
both are disabled.
Once the chip is placed in overwrite disable mode, it remains disabled against overwriting unless
the Overwrite Enable instruction is entered.
TC9WMA1FK
2001-10-16
4
3. Precautions to be Taken at Power ON/OFF
(1) A wait time of 1 ms is required before the chip starts operation after it is powered on.
(2)
RST
must be pulled low when the power to the chip turns ON or OFF.
(3) The chip is placed in overwrite disable mode by reset.
4. Timing Chart
(1) Read
(2) Program
CS
CLK
1 2
7 8 9
10
11
12
13
14
15
16
17
24
23
A0 A1
0
0 1
0
1
0
0
0
0
DI
DO
Command
Address
Hi-Z
A6
D6 D7
D0
CS
CLK
1 2
7 8 9
10
11
12
13
14
15
16
17
24
23
A0 A1
1
0 0
0
0
0
0
0
0
DI
DO
Hi-Z
Command
Address
Hi-Z
A6
D0
Data
D6 D7
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