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Электронный компонент: TMP91C630AD

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TOSHIBA Original CMOS 16-Bit Microcontroller
TLCS-900/L1 Series
TMP91C630















Preface


Thank you very much for making use of Toshiba microcomputer LSIs.
Before use this LSI, refer the section, "Points of Note and Restrictions".
TMP91C630
2003-07-22
91C630-1
CMOS 16-Bit Microcontrollers
TMP91C630F
1.
Outline and Features
TMP91C630 is a high-speed 16-bit microcontroller designed for the control of various mid- to
large-scale equipment. 2 Kbytes of boot ROM is built-in. The standard name of this microcontroller
is TMP91C630F-7770 with ROM code (7770).
The package of TMP91C630 is 100-pin flat type. The features are shown below.
(1) High-speed 16-bit CPU (900/L1 CPU)
Instruction mnemonics are upward-compatible with TLCS-90/900
16 Mbytes of linear address space
General-purpose registers and register banks
16-bit multiplication and division instructions; bit transfer and arithmetic instructions
Micro DMA: Four-channels (444 ns/2 bytes at 36 MHz)
(2) Minimum instruction execution time: 111 ns (at 36 MHz)
(3) Built-in RAM: 6 Kbytes
Built-in ROM: None
Built-in Boot ROM: 2 Kbytes
(4) External memory expansion
Expandable up to 16 Mbytes (shared program/data area)
Can simultaneously support 8-/16-bit width external data bus
Dynamic data bus sizing
(5) 8-bit timers: 6 channels
(6) 16-bit timer/event counter: 1 channel
(7) Serial bus interface: 2 channels
(8) 10-bit AD converter: 8 channels
(9) Watchdog timer
The information contained herein is subject to change without notice.
The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of TOSHIBA or others.
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for
Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made
at the customer's own risk.
The products described in this document are subject to the foreign exchange and foreign trade laws.
TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law
and regulations.
For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality
and Reliability Assurance/Handling Precautions.
030619EBP1
TMP91C630
2003-07-22
91C630-2
(10) Chip Select/Wait controller: 4 blocks
(11) Interrupts: 35 interrupts
9 CPU interrupts: Software interrupt instruction and illegal instruction
19 internal interrupts: 7 priority levels are selectable.
7 external interrupts: 7 priority levels are selectable.
(Level mode, rising edge mode and falling edge mode are selectable.)
(12) Input/output ports: 53 pins
(13) Standby function
Three halt modes: Idle2 (programmable), Idle1, Stop
(14) Operating voltage
VCC 2.7 V to 3.6 V (fc max 36 MHz)
(15) Package
100-pin QFP: P-LQFP100-1414-0.50F
TMP91C630
2003-07-22
91C630-3














































Figure 1.1 TMP91C630 Block Diagram
ADTRG
(AN3/PA3)
AN0~AN7 (PA0~PA7)
VREFH
VREFL
AVCC
AVSS






RD
WR
PZ2 (
HWR
)
PZ3
TXD0 (P80)
RXD0 (P81)
SCLK0/
CTS0
(P82)
0
STS
(P83)
TXD1 (P84)
RXD1 (P85)
SCK1/
1
CTS
(P86)
1
STS
(P87)
TA0IN/INT1 (P70)
TA1OUT (P71)
TA3OUT/INT2 (P72)
TA4IN/INT3 (P73)
TA5OUT (P74)
INT4 (P75)
DVCC [4]
DVSS [4]
BOOT
AM0/AM1
RESET
X1
X2
EMU0
EMU1
(P10~P17) D8~D15

(P20~P27) A16~A23

D0~D7

A0~A7
A8~A15

BUSRQ
(P53)
BUSAK
(P54)




WAIT
(P55)
CS0
(P60)
CS1
(P61)
CS2
(P62)
3
CS
(P63)
NMI
INT0 (P56)




TB0IN0 (P93)
TB0IN1 (P94)
TB0OUT0 (P95)
TB0OUT1 (P96)
INT5 (P90)
10-bit 8-ch
AD
converter
Port A
8-bit timer
(TMRA0)
Port Z
8-bit timer
(TMRA1)
8-bit timer
(TMRA2)
8-bit timer
(TMRA3)
Serial I/O
(channel 0)
OSC
Clock gear
Port 1
CS/WAIT
controller
(4 blocks)
Address bus
Interrupt
controller
16-bit timer
(TMRB0)
Data bus
Port 9




6-KB RAM
Watchdog timer
(WDT)
XWA
XBC
XDE
XHL
XIX
XIY
XIZ
XSP
W
A
B
C
D
E
H
L
IX
IY
IZ
SP
32 bits
SR
PC
F
CPU (TLCS-900L1)
Port 2
2-KB boot ROM
Port 5
Serial I/O
(channel 1)
Port 8
8-bit timer
(TMRA4)
8-bit timer
(TMRA5)
Port 7