TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.

TX39

/TX49

RISCASIC

Cores

32/64-bit MIPS

Description

Toshiba offers 32/64-bit CPU and peripheral cores based
on the architecture pioneered by MIPS

Technologies

Inc. These cores come in varied speeds and sizes to help
customers achieve the best price performance solution in
their ASIC implementation.

Toshiba has been supporting customers with CPU core
and peripherals embedded in ASICs for many years with
a solid track record of successful RISCASICs in
consumer, communications and computer applications.
These cores have also been implemented in high volume
ASSP products and are fully supported with software and
hardware development tools.

TX39 CPU Core Features

The TX39 family includes the TC220, 240 and 260 ASIC
families and offers a high performance 32- bit processor
up to 133 MHz in an ASIC-ready hard core. It has
applications in digital signal processing fields with a
single-cycle Multiply Accumulate (MAC) operation. A
debug support unit is also available on the core.

· 5-Stage Pipeline

· MIPS I Instruction Set Architecture (ISA)

· Non-Blocking Load

· Instruction Cache: 8K/4K Bytes, 2-Way Set Associative

· Data Cache: 4K/1K Bytes, 2-Way Set Associative

· 64 -Entry MMU/TLB: 4K Byte to 4M Byte pages

TX49 CPU Core Features

The TX49 family is a high-end 64-bit processor offering

up to 180 MHz ASIC-ready hard core. These cores are

available in TC240 and 260 families with cache and FPU

options.

· 5-Stage Pipeline (optimized)

TOSHIBA

· MIPS I, II and III Instruction Set Architecture (ISA)

· Multiply, Accumulate (MAC) and Prefetch (PREF)

instructions

· 32, 64-bit integer general purpose register

· 32, 32-bit floating point general purpose registers

· Instruction Cache: 16K/32K Bytes (option), 4-Way Set

Associative and Lock function support

· Data Cache: 16K/32K Bytes (option), 4-Way Set

Associative and Lock function support, Write back and
Write through support

· 48 -Entry MMU: 48-double entry JTLB, 2-entry

Instruction TLB, 4-entry Data TLB

· Optional Floating Point Unit (IEEE 754 Std. Double

precision)

· Debug Support Unit with Enhanced JTAG support

TX39/49 Peripherals

These peripherals support up to 64 Mb DRAM and are

available as soft cores.

· DRAM, Memory & DMA Controller

· Timer

· Serial I/O

· PCI

CPU Core Lineup

Following table shows the list of CPU Cores and their
relevant features:

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TX49 Core

Integer Unit

Floating-Point

Coprocessor (CP1)

System Control

Coprocessor (CP0)

GPR

MAC

Data
Path

Pipeline

Controller

Cache

Controller

32K Byte

4-way Set

Instruction

Cache

32K Byte

4-way Set Data

Cache

Write Buffer

CP1 Registers

Data Path

CP0 Registers

MMU w/ TLB

Exception Unit

TX49 Core Diagram

Core

Clock

Speed

Family

Geometry

TX39/H

TX39/H2

TX49H

TX49H2

70Mhz

100Mhz

133Mhz

150Mhz

180Mhz

TC220

0.35

µm

CMOS

TX39/H3

TC240

TC260

TC240

TC260

0.25

µm

CMOS

0.14

µm

CMOS

0.25

µm

CMOS

0.14

µm

CMOS

RISCASIC Core & Peripherals Block Diagram

TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.

Evaluation Board

The Evaluation Board (EVAL Board) and debug monitor
enables the user to execute, evaluate and debug user
programs. It connects to the debugger via serial
interface. The EVAL board uses an application specific
standard product (ASSP) that was designed for the
corresponding CPU core.

Hardware and Software Co-Development

The user is able to co-develop software and hardware
using a third party products from CAE Plus

or Mentor

Graphics

. To improve the debugging process the user

is able to co-verify the operation of these modules by
performing proper partitioning of hardware and software.
Mentor's SeamlessTM product provides full run control
through software/hardware break points and allows
different event recognizers to generate triggers for their
collection.

Summary

Today's deep sub-micron ASIC technologies are capable
of millions of gates and permit high levels of System
Level Integration (SLI) consisting of memory,
microprocessors, analog functions, application logic and
I/Os on one chip. SLI ASIC design success means
getting through development and into production on-time
while keeping development costs and device price low.
The challenge is to employ the best mix of ASIC
technology, design flow and methodology, EDA tools,
libraries and packaging matched for the job. With many
years of serving ASIC customers, Toshiba provides all
the capabilities needed for success.

Toshiba offers embedded arrays for fast turn around
times when special blocks such as RAM, ROM or RISC
CPUs are needed or standard cell approach is available
for the lowest device costs and best chip performance.
Toshiba's design flow is based on commercially available
EDA tools and includes Toshiba's Timing-Driven Flow
(TDF). Our broad packaging capabilities include thermally
enhanced and low profile QFPs and BGAs with high pin
count. Toshiba is committed to the fastest proto-typing
and ramp-to-production in the industry across all ASICs
and our high capacity manufacturing facilities are
ISO9001 certified. With these capabilities, Toshiba can
make sure that you get your chips out on-time and meet
your specifications with the lowest cost and risk.

Application Specific Standard Products
(ASSPs)

Toshiba offers ASSPs to help customers understand the
features of the CPU and peripheral cores. The following
diagram shows the list of the ASSPs and their
peripherals:

Development Tools

A complete range of hardware and software tools are
available from Toshiba and third party tool vendors. The
development environment includes a C-Compiler,
simulator, Evaluation Board, In Circuit Emulator (ICE) and
Real Time Operating System (RTOS). The environment
provides full support for program and debugging during
application development. These tools can also be used in
conjunction with a third-party development system.

C-Compiler

C/C++ Compilers for the MIPS family are available from
Cygnus

. Position independent code can be specified

and 16/32/64-bit ISA instruction sets are supported.
Operating systems Windows 95, NT 4.0 or Solaris can be
supported.

Simulator

The simulator has a simple, high-speed instruction set
and keeps log of executed instructions. It allows the
tracing of status changes in the CPU registers. Target
hardware is not required.

Debugger

The debugger features a Graphical User Interface (GUI)
which controls the simulator, emulator and debug
monitor. It supports a "drop and drag" feature, inter-
window access and Windows 95 or NT 4.0
environments. The debugging system uses the JTAG
feature and communicates serially with the target chip
(RISCASIC). Break points and trace can be set through
debug pins.

TOSHIBA

NORTHWEST
San Jose, CA
TEL: (408) 526-2400
FAX: (408) 526-2410

Portland, OR
TEL: (503) 629-0818
FAX: (503) 629-0827

SOUTHWEST
Irvine, CA
TEL: (949) 461-3800
FAX: (949) 768-2918

Dallas, TX
TEL: (972) 480-0470
FAX: (972) 235-4114

CENTRAL
Chicago, IL
TEL: (847) 945-1500
FAX: (847) 945-1044

NORTHEAST
Boston, MA
TEL: (781) 224-0074
FAX: (781) 224-1096

Edison, NJ
TEL: (732) 248-8070
FAX: (732) 248-8030

SOUTHEAST
Atlanta, GA
TEL: (770) 931-3363
FAX: (770) 931-7602

TAEC Regional Sales Offices

The technical data may be controlled under U.S. Export Administration Regulations and may be subject to the approval of the U.S. Department of Commerce prior to export. Any export or re-
export directly or indirectly, in contravention of the U.S. Export Administration regulations, is strictly prohibited.

Toshiba,TX39, TX49 and RISCASIC are all trademarks of Toshiba Corporation. MIPS is a registered trademark of MIPS Technologies Inc. Cygnus
is a registered trademark of Red Hat, Inc. CAE Plus is a registered trademark of CAE Plus Inc. Seamless is a trademark and Mentor Graphics is a
registered trademark of Mentor Graphics.All others are trademarks of their respective manufacturer and may be registered in certain jurisdictions.

3903A

3912

3927AF

4927

ASSP FPU ROMC DMAC DRAMC PCI IRC Timer SIO PIO UART

X
X

4955

3904AF

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