T E C H N I C A L I N F O R M A T I O N
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TA2020-020, Rev. 4.0, 09.00
Stereo 20W (4
) Class-T Digital Audio Amplifier using
Digital Power Processing
TM
Technology
TA2020-020
September, 2000
General Description
The TA2020-020 is a 20W continuous average two-channel Class-T Digital Audio Power
Amplifier IC using Tripath's proprietary Digital Power Processing
TM
technology. Class-T
amplifiers offer both the audio fidelity of Class-AB and the power efficiency of Class-D
amplifiers.
Applications
DVD Players
Mini/Micro Component Systems
Automotive Audio
Computer / PC Multimedia
Cable Set-Top Products
Televisions
Battery Powered Systems
Benefits
Fully integrated solution with FETs
Easier to design-in than Class-D
Reduced system cost with no heat sink
Dramatically improves efficiency versus
Class-AB
Signal fidelity equal to high quality linear
amplifiers
High dynamic range compatible with
digital media such as CD, DVD, and
internet audio
Features
Class-T architecture
Single Supply Operation
"Audiophile" Quality Sound
0.03% THD+N @ 10W 4
0.1% THD+N @12W 4
0.18% IHF-IM @ 1W 4
High Power
13W @ 8
, 10% THD+N
23W @ 4
, 10% THD+N
38W EIAJ* VDD=14.4V @ 4
*saturated square wave output
High Efficiency
88% @ 12W 8
81% @ 20W 4
Dynamic Range = 103 dB
Up to 2
X
25Wrms @ 4
, V
DD
=14.6V
Mute and Sleep inputs
Turn-on & turn-off pop suppression
Over-current protection
Over-temperature protection
Bridged outputs
32-pin SSIP package
Typical Performance
THD+N (%)
Output Power (W)
THD+N versus Output Power
VDD = 13.5V
Av = 12
f = 1kHz
BW = 22Hz - 22kHz
1
2
3
4
5 6 7 8 9 10
20
500m
R
L
= 8
R
L
= 4
1
2
5
0.02
0.01
0.05
0.1
0.2
0.5
10
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Absolute Maximum Ratings
(Note 1)
SYMBOL PARAMETER
Value
UNITS
V
DD
Supply Voltage
16
V
T
STORE
Storage Temperature Range
-40
to 150
C
T
A
Operating Free-air Temperature Range
-40
to 85
C
T
J
Junction Temperature
150
C
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Operating Conditions
(Note 2)
SYMBOL PARAMETER MIN.
TYP.
MAX.
UNITS
V
DD
Supply Voltage
8.5
13.5
14.6
V
V
IH
High-level Input Voltage (MUTE, SLEEP)
3.5
V
V
IL
Low-level Input Voltage (MUTE, SLEEP)
1
V
Note 2: Recommended Operating Conditions indicate conditions for which the device is functional.
See Electrical Characteristics for guaranteed specific performance limits.
Thermal Characteristics
SYMBOL PARAMETER
Value
UNITS
JC
Junction-to-case Thermal Resistance
3.5
C/W
JA
Junction-to-ambient Thermal Resistance
15
C/W
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Electrical Characteristics
(Note 1, 2)
See Test/Application Circuit. Unless otherwise specified, V
DD
= 13.5V, f = 1kHz, Measurement
Bandwidth = 22kHz, R
L
= 4
, T
A
= 25
C.
SYMBOL PARAMETER
CONDITIONS MIN.
TYP.
MAX.
UNITS
P
O
Output Power
(Continuous Average/Channel)
THD+N = 0.1%
R
L
= 4
R
L
= 8
THD+N = 10%
R
L
= 4
R
L
= 8
13
8
22
12
W
W
W
W
I
DD,MUTE
Mute Supply Current
MUTE = V
IH
5.5
7
mA
I
DD, SLEEP
Sleep Supply Current
SLEEP = V
IH
0.25
2
mA
I
q
Quiescent Current
V
IN
= 0 V
60
mA
THD + N Total Harmonic Distortion Plus
Noise
P
O
= 10W/Channel
0.03
%
IHF-IM
IHF Intermodulation Distortion
19kHz, 20kHz, 1:1 (IHF)
0.18
%
SNR Signal-to-Noise
Ratio
A-Weighted, P
OUT
= 1W, R
L
= 8
89
dB
CS Channel
Separation
0dBr = 1W, R
L
= 4
, f = kHz
74 80 dB
PSRR
Power Supply Rejection Ratio
Vripple = 100mV
60
80
dB
Power Efficiency
P
OUT
= 12W/Channel, R
L
= 8
88 %
V
OFFSET
Output Offset Voltage
No Load, MUTE = Logic low
50
150
mV
V
OH
High-level output voltage
(FAULT & OVERLOADB)
3.5
V
V
OL
Low-level output voltage
(FAULT & OVERLOADB)
1
V
e
OUT
Output Noise Voltage
A-Weighted, input AC grounded
100
V
Notes:
1) Minimum and maximum limits are guaranteed but may not be 100% tested.
2) For operation in ambient temperatures greater than 25
C, the device must be derated based on
the maximum junction temperature and the thermal resistance determined by the mounting
technique.
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Pin Description
Pin
Function
Description
2, 8
V5D, V5A
Digital 5VDC, Analog 5VDC
3, 7,
16
AGND1, AGND2,
AGND3
Analog Ground
4
REF
Internal reference voltage; approximately 1.0VDC
6
OVERLOADB
A logic low output indicates the input signal has overloaded the amplifier.
9, 12
VP1, VP2
Input stage output pins
10, 13
IN1, IN2
Single-ended inputs. Inputs are a "virtual" ground of an inverting opamp with
approximately 2.4VDC bias.
11
MUTE
When set to logic high, both amplifiers are muted and in idle mode. When low
(grounded), both amplifiers are fully operational. If left floating, the device stays in
the mute mode. Ground if not used.
14
BIASCAP
Input stage bias voltage (approximately 2.4VDC).
17
SLEEP
When set to logic high, device goes into low power mode. If not used this pin
should be grounded.
18
FAULT
A logic high output indicates thermal overload, or an output is shorted to ground,
or another output.
19, 28
PGND2, PGND1
Power Ground (high current)
20 DGND
Digital
Ground
21, 23,
26, 24
OUTP2 & OUTM2;
OUTP1 & OUTM1
Bridged outputs
22, 25
VDD2, VDD1
Supply pin for high current H-bridges, nominally 13.5VDC.
1, 5, 15
NC
Not connected
27 VDDA
Analog
13.5VDC
29
CPUMP
Charge pump output (nominally 10V above VDDA)
30
5VGEN
Regulated 5VDC source used to supply power to the input section (pins 2 & 8).
31, 32
DCAP2, DCAP1
Charge pump switching pins. DCAP1 (pin 32) is a free running 300kHz square
wave between VDDA and DGND (13.5Vpp nominal). DCAP2 (pin 31) is level
shifted 10 volts above DCAP1 (pin 32) with the same amplitude (13.5Vpp
nominal), frequency, and phase as DCAP1.
5VGEN
NC
FAULT
PGND2
DGND
OUTP2
VDD2
OUTM2
OUTM1
VDD1
OUTP1
NC
VDDA
PGND1
CPUMP
DCAP2
AGND3
BIASCAP
IN2
VP2
MUTE
IN1
VP1
V5A
AGND2
OVERLOADB
REF
AGND1
V5D
DCAP1
30
16
17
18
19
20
21
22
23
24
25
26
27
28
29
1
15
14
13
11
10
12
9
8
7
6
5
4
3
2
32-pin SSIP Package
(Front View)
32
31
SLEEP
NC
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Application/Test Circuit
TA2020-020
R
L
4 or *8
MUTE
FAULT
OVERLOADB
(+13.5V)
C
I
2.2uF
VP1
VP2
IN1
IN2
OUTP1
OUTM1
OUTP2
OUTM2
VDDA
5VGEN
BIASCAP
DCAP2
DCAP1
C
I
2.2uF
C
A
0.1uF
C
D
0.1uF
CPUMP
9
10
19
30
27
25
22
6
18
26
24
21
23
29
31
32
13
12
11
14
R
F
20K
17
R
Z
10, 1/2W
C
Z
0.47uF
C
P
1uF
+
+
5V
SLEEP
5V
5V
+12V
0.1uF
REF
R
REF
8.25K, 1%
4
5
NC
1meg
All Diodes Motorola MBRS130T3
* Use C
o
= 0.22F for 8 Ohm loads
VDD1
PGND1
VDD1
PGND1
VDD2
VDD2
PGND2
PGND2
Note: Analog and Digital/Power Grounds must
be connected locally at the TA2020-020
C
S
0.1uF
C
S
0.1uF
To Pin 30
2
3
V5D
7
15
AGND1
AGND2
V5A
20
C
S
0.1uF
DGND
VDD1
PGND2
28
PGND1
180uF, 16V
VDD2
VDD
+
+
+
Processing
&
Modulation
Processing
&
Modulation
*C
o
0.47uF
L
o
10uH, 3A
8
(Pin 7)
Analog Ground
Digital/Power Ground
(Pin 28)
(Pin 28)
(Pin 19)
(Pin 19)
To Pin 2,8
R
I
20K
(Pin 3)
R
F
20K
R
I
20K
1
NC
NC
AGND3
16
180uF, 16V
C
SW
C
SW
*C
o
0.47uF
L
o
10uH, 3A
R
L
4 or *8
L
o
10uH, 3A
L
o
10uH, 3A
*C
o
0.47uF
*C
o
0.47uF
C
Z
0.47uF
C
SW
0.1uF
C
SW
0.1uF
C
S
0.1uF
D
O
D
O
D
O
D
O
C
CM
0.1uF
C
CM
0.1uF
R
Z
10, 1/2W
(Pin 28)
(Pin 19)
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External Components Description
(Refer to the Application/Test Circuit)
Components Description
R
I
Inverting input resistance to provide AC gain in conjunction with R
F
. This input is
biased at the BIASCAP voltage (approximately 2.4VDC).
R
F
Feedback resistor to set AC gain in conjunction with R
I
;
)
R
/
R
(
12
A
I
F
V
=
. Please refer
to the Amplifier Gain paragraph, in the Application Information section.
C
I
AC input coupling capacitor which, in conjunction with R
I
, forms a highpass filter at
)
C
R
2
(
1
f
I
I
C
=
R
REF
Bias resistor. Locate close to pin 4 and ground at pin 7.
C
A
BIASCAP decoupling capacitor. Should be located close to pin 14 and grounded at
pin 7.
C
D
Charge pump input capacitor. This capacitor should be connected directly between
pins 31 and 32 and located physically close to the TA2020-020.
C
P
Charge pump output capacitor that enables efficient high side gate drive for the
internal H-bridges. To maximize performance, this capacitor should be connected
directly between pin 29 (CPUMP) and pin 27 (VDDA). Please observe the polarity
shown in the Application/Test Circuit.
C
S
Supply decoupling for the low current power supply pins. For optimum performance,
these components should be located close to the pin and returned to their
respective ground as shown in the Application/Test Circuit.
C
SW
Supply decoupling for the high current H-Bridge supply pins. These components
must be located as close to the device as possible to minimize supply overshoot and
maximize device reliability. Both the high frequency bypassing (0.1uF) and bulk
capacitor (180uF) should have good high frequency performance including low ESR
and low ESL. Panasonic HFQ or FC capacitors are ideal for the bulk capacitor.
C
Z
Zobel capacitor, which in conjunction with R
Z
, terminates the output filter at high
frequencies
R
Z
Zobel resistor, which in conjunction with C
Z
, terminates the output filter at high
frequencies. The combination of R
Z
and C
Z
minimizes peaking of the output filter
under both no load conditions or with real world loads, including loudspeakers which
usually exhibit a rising impedance with increasing frequency. Depending on the
program material, the power rating of R
Z
may need to be adjusted. The typical value
is watt.
D
O
Schottky diodes that minimize undershoots of the outputs with respect to power
ground during switching transitions. For maximum effectiveness, these diodes must
be located close to the output pins and returned to their respective PGND. Please
see Application/Test Circuit for ground return pin.
L
O
Output inductor, which in conjunction with C
O
, demodulates (filters) the switching
waveform into an audio signal. Forms a second order filter with a cutoff frequency
of and a quality factor of
O
O
O
L
C
L
C
R
Q
=
.
C
O
Output capacitor which in conjunction with L
O
, demodulates (filters) the switching
waveform into an audio signal. Forms a second order low-pass filter with a cutoff
frequency of
)
C
L
2
(
1
f
O
O
C
=
and a quality factor of
O
O
O
L
C
L
C
R
Q
=
.
C
CM
Common mode capacitor.
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Typical Performance Characteristics
Output Amplitude (dBr)
Frequency (Hz)
Frequency Response
VDD = 13.5V
Pout = 1W
RLoad = 4
Av = 12
BW = 22Hz - 22kHz
-2
+2
-1.5
-1
-0.5
+0
+0.5
+1
+1.5
+2.5
+3
-2.5
-3
10
20k
20
50
100
200
500
1k
2k
5k
10k
THD+N (%)
Frequency (Hz)
THD+N versus Frequency
10
20k
20
50
100
200
500
1k
2k
5k
10k
VDD = 13.5V
Pout = 5W/Channel
Av = 12
BW = 22Hz - 22kHz
10
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
R
L
= 4
R
L
= 8
Noise Floor
Frequency (Hz)
Noise FFT (dBV)
20
20k
50
100
200
500
1k
2k
5k
10k
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
-150
VDD = 13.5V
Pout = 0W
Av = 12
RLoad = 4
BW = 20Hz - 22kHz
A-Weighted Filter
Intermodulation Performance
Frequency (Hz)
FFT (dBr)
50
30k
1k
2k
5k
10k
20k
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
VDD = 13.5V
Pout = 1W/Channel
RLoad = 4W
19kHz, 20kHz, 1:1
0dBr = 12Vrms
Av = 12
BW = 10Hz - 80kHz
Channel Separation versus Frequency
Frequency (Hz)
Channel Separation (dBr)
VDD = 13.5V
Pout = 1W/Channel
RLoad = 4
Av = 12
BW = 22Hz - 22kHz
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20
20k
50
100
200
500
1k
2k
5k
10k
Efficiency versus Output Power
0
10
20
30
40
50
60
70
80
90
100
0
5
10
15
20
25
30
Output Power (W)
Efficiency (%)
R
L
= 4
R
L
= 8
VDD = 13.5V
f = 1kHz
Av = 12
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TA2020-020, Rev. 4.0, 09.00
Application Information
Circuit Board Layout
The TA2020-020 is a power (high current) amplifier that operates at relatively high switching
frequencies. The outputs of the amplifier switch between the supply voltage and ground at high
speeds while driving high currents. This high-frequency digital signal is passed through an LC low-
pass filter to recover the amplified audio signal. Since the amplifier must drive the inductive LC
output filter and speaker loads, the amplifier outputs can be pulled above the supply voltage and
below ground by the energy in the output inductance. To avoid subjecting the TA2020-020 to
potentially damaging voltage stress, it is critical to have a good printed circuit board layout. It is
recommended that Tripath's layout and application circuit be used for all applications and only be
deviated from after careful analysis of the effects of any changes.
The figures below are the Tripath TA2020-020 evaluation board. Some of the most critical
components on the board are the power supply decoupling capacitors. C674 and C451 must be
placed right next to pins 22 and 19 as shown. C673 and C451B must be placed right next to pins
25 and 28 as shown. These power supply decoupling capacitors from the output stage not only
help reject power supply noise, but they also absorb voltage spikes on the VDD pins caused by
overshoots of the outputs of the amplifiers. Voltage overshoots can also be caused by output
inductor flyback during high current switching events such as shorted outputs or driving low
impedances at high levels. If these capacitors are not close enough to the pins, electrical
overstress to the part can occur, possibly resulting in permanent damage to the TA2020-020.
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Amplifier Gain
The gain of the TA2020-020 is set by the ratio of two external resistors, R
I
and R
F
, and is given by
the following formula:
I
F
I
O
R
R
12
V
V
=
where V
I
is the input signal level and V
O
is the differential output signal level across the speaker.
20 watts of RMS output power results from an 8.944 V RMS signal across a four-ohm speaker load.
If R
F
= R
I
, then 20 Watts will be achieved with 0.745 V RMS of input signal.
)
W
20
4
(
)
P
R
(
V
944
.
8
O
L
RMS
=
=
Protection Circuits
The TA2020-020 is guarded against over-temperature and over-current conditions. When the
device goes into an over-temperature or over-current state, the FAULT pin goes to a logic HIGH
state indicating a fault condition. When this occurs, the amplifier is muted, all outputs are TRI-
STATED, and will float to 1/2 of V
DD
.
Over-temperature Protection
An over-temperature fault occurs if the junction temperature of the part exceeds approximately
155
C. The thermal hysteresis of the part is approximately 45C, therefore the fault will
automatically clear when the junction temperature drops below 110
C.
Over-current Protection
An over-current fault occurs if more than approximately 7 amps of current flows from any of the
amplifier output pins. This can occur if the speaker wires are shorted together or if one side of the
speaker is shorted to ground. An over-current fault sets an internal latch that can only be cleared if
the MUTE pin is toggled or if the part is powered down. Alternately, if the MUTE pin is connected to
the FAULT pin, the HIGH output of the FAULT pin will toggle the MUTE pin and automatically reset
the fault condition.
Overload
The OVERLOADB pin is a 5V logic output. When low, it indicates that the level of the input signal
has overloaded the amplifier resulting in increased distortion at the output. The OVERLOADB
signal can be used to control a distortion indicator light or LED through a simple buffer circuit.
Sleep Pin
The SLEEP pin is a 5V logic input that when pulled high (>3.5V) puts the part into a low quiescent
current mode. This pin is internally clamped by a zener diode to approximately 6V thus allowing the
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TA2020-020, Rev. 4.0, 09.00
pin to be pulled up through a large valued resistor (1M
recommended) to V
DD
. To disable SLEEP
mode, the sleep pin should be grounded.
Fault Pin
The FAULT pin is a 5V logic output that indicates various fault conditions within the device. These
conditions include: low supply voltage, low charge pump voltage, low 5V regulator voltage, over
current at any output, and junction temperature greater than approximately 155
C. The FAULT
output is capable of directly driving an LED through a series 200
. The FAULT output is capable of
directly driving an LED through a series 200
resistor. If the FAULT pin is connected directly to the
MUTE input an automatic reset will occur in the event of an over-current condition.
Heat Sink Requirements
In some applications it may be necessary to fasten the TA2020-020 to a heat sink. The determining
factor is that the 150
C maximum junction temperature, T
J
(max) cannot be exceeded, as specified
by the following equation:
P
DISS
=
(
)
JA
A
)
MAX
(
J
T
T
-
where...
P
DISS
= maximum power dissipation
T
JMAX
= maximum junction temperature of TA2020-020
T
A
= operating ambient temperature
JC
= junction-to-case thermal resistance of TA2020-020
Example:
What size heat sink is required to operate the TA2020-020 at 20W per channel continuously in a
70C ambient temperature?
P
DISS
is determined by:
Efficiency
=
=
IN
OUT
P
P
=
DISS
OUT
OUT
P
P
P
-
P
DISS
(per channel) =
W
5
20
8
.
0
20
P
P
OUT
OUT
=
-
=
-
Thus,
P
DISS
for two channels = 10W
JA
=
(
)
DISS
A
)
MAX
(
J
P
T
T
-
=
10
70
150
-
= 8
C/W
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The
JA
of the TA2020-020 in free air is 15
C/W. The
JC
of the TA2020-020 is 3.5
C/W, so a heat
sink of 4.5
C/W is required for this example. In actual applications, other factors such as the
average P
DISS
with a music source (as opposed to a continuous sine wave) and regulatory agency
testing requirements will determine the size of the heat sink required.
Performance Measurements of the TA2020-020
The TA2020-020 operates by generating a high frequency switching signal based on the audio
input.
This signal is sent through a low-pass filter (external to the Tripath amplifier) that recovers an
amplified version of the audio input
.
The frequency of the switching pattern is spread spectrum in
nature and typically varies between 100kHz and 1MHz, which is well above the 20Hz 20kHz
audio band. The pattern itself does not alter or distort the audio input signal, but it does introduce
some inaudible components.
The measurements of certain performance parameters, particularly noise related specifications
such as THD+N, are significantly affected by the design of the low-pass filter used on the output as
well as the bandwidth setting of the measurement instrument used. Unless the filter has a very
sharp roll-off just beyond the audio band or the bandwidth of the measurement instrument is limited,
some of the inaudible noise components introduced by the TA2020-020 amplifier switching pattern
will degrade the measurement.
One feature of the TA2020-020 is that it does not require large multi-pole filters to achieve excellent
performance in listening tests, usually a more critical factor than performance measurements.
Though using a multi-pole filter may remove high-frequency noise and improve THD+N type
measurements (when they are made with wide-bandwidth measuring equipment), these same
filters degrade frequency response. The TA2020-020 Evaluation Board uses the Application/Test
Circuit of this data sheet, which has a simple two-pole output filter and excellent performance in
listening tests. Measurements in this data sheet were taken using this same circuit with a limited
bandwidth setting in the measurement instrument.
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Package Information
32-pin SSIP Package:
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TA2020-020, Rev. 4.0, 09.00
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ADVANCED INFORMATION This is a product in development. Tripath Technology Inc. reserves
the right to make any changes without further notice to improve reliability, function or design.
Tripath and Digital Power Processing are trademarks of Tripath Technology Inc. Other trademarks
referenced in this document are owned by their respective companies
.
Tripath Technology Inc. reserves the right to make changes without further notice to any products
herein to improve reliability, function or design. Tripath does not assume any liability arising out of
the application or use of any product or circuit described herein; neither does it convey any license
under its patent rights, nor the rights of others.
TRIPATH'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN
LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN CONSENT OF
THE PRESIDENT OF TRIPATH TECHNOLOGY INC. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical
implant into the body, or (b) support or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in this labeling, can be reasonably
expected to result in significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to
perform can be reasonably expected to cause the failure of the life support device or system, or
to affect its safety or effectiveness.
For more information on Tripath products, visit our web site at: www.tripath.com
World Wide Sales Offices
Western United States: Jim Hauer
jhauer@tripath.com
408-567-3089
Taiwan, HK, China:
Jim Hauer
jhauer@tripath.com
408-567-3089
Japan: Osamu
Ito
ito@tripath.com
81-42-334-2433
Europe: Steve
Tomlinson
stomlinson@tripath.com
44-1672-86-1020
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TRIPATH TECHNOLOGY, INC.
3900 Freedom Circle, Suite 200
Santa Clara, California 95054
408-567-3000
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