T r i p a t h T e c h n o l o g y, I n c . - T e c h n i c a l I n f o r m a t i o n
1
TLD4012 JB/Rev. 2.0a/05.02
TLD4012
A D S L L I N E D R I V E R U S I N G T R I P A T H D I G I T A L P O W E R
P R O C E S S I N G ( D P P TM ) T E C H N O L O G Y
T e c h n i c a l I n f o r m a t i o n R e v i s i o n 2 . 0 a M a y 2 0 0 2
G E N E R A L D E S C R I P T I O N
T h e T L D 4 0 1 2 i s a n A D S L l i n e d r i v e r t h a t p r o v i d e s v e r y l o w p o w e r c o n s u m p t i o n a n d
l o w d i s t o r t i o n i n a v e r y s m a l l p a c k a g e a s a r e s u l t o f T r i p a t h ' s p r o p r i e t a r y p o w e r
p r o c e s s i n g t e c h n o l o g y . T h i s d e v i c e a c c e p t s d i f f e r e n t i a l i n p u t s i g n a l s f r o m a n a n a l o g
f r o n t - e n d ( A F E ) , a n d c a n b e u s e d i n f u l l - r a t e ( G . d m t ) , o r G . l i t e s y s t e m s . T h i s T L D 4 0 1 2
o f f e r s a l o w p o w e r c o n s u m p t i o n o f 6 5 0 m W f o r f u l l - r a t e , f u l l - p o w e r , C O - s i d e , F D M
( n o n - o v e r l a p p e d ) t r a n s m i s s i o n s .
A P P L I C A T I O N S
Full-rate or G.lite line cards
DSLAMs
DLC equipment
Central office switches
B E N E F I T S
Reduced line card power
Reduced system power
Increased line card density
More ports per cubic foot of system
space
Improved system performance
Simplifies thermal management on
PCB
Improved reliability
Flexible solution
F E A T U R E S
Tripath Proprietary Power Processing technology
Very low power consumption
P
CONS
(Full-rate ADSL) = 650 mW (typ)
P
CONS
(G.lite) = 390 mW (typ)
Low distortion
Spurious free dynamic range = -80 dBc 26kHz to 138kHz,
R
LINE
=100
, P
LINE
=19.8dBm
Third harmonic distortion = -83 dBc at f = 100 kHz,
-82 dBc at f = 500 kHz, -63 dBc at f = 1 MHz, V
OUT
= 10Vpp
(differential), 70
load
500 mA minimum output current into a 71
load
Digitally programmable gain (from 12.8 to 27.8 dB in 1 dB steps)
Low-power mode -130 mW typical (line terminated -allows
reception of incoming signals)
Disabled mode - 10 mW typical (no line termination)
Over-temperature and over-current protection with Fault output
5x5 mm 32-pin TQFP with exposed die pad
Power
Processing
Block
INP
Control
&
Logic
Output
current
limit
LOPWR
RESETB
G0
G1
G2
INN
VDD5
GND
FAULT
R
EXT
OUTN
OUTP
VSS15
VDD15
VSS5
3
20
21
16
25
15
14
28
6
7
8
4
23
27
13
12
18
11
Block Diagram
G3 9
EN_AC 1
FORC_BIAS
TH_FAULT
AUTO_CLR 31
FBP
30
FBN
29
GND
5
2
GND
INP
GND
EN_AC
NC
OUTP
NC
VDD15
NC
OUTN
NC
VSS15
24
17
18
19
20
21
22
23
1
8
7
6
5
4
3
2
(Top View)
G2
G0
G1
GND
INN
32
31
30
29
28
27 26 25
1
9
10 11 12 13
14 15 16
NC
A
UT
O
_
CL
R
FB
P
FB
N
GN
D
R
EX
T
NC
VDD5
G3
FAU
L
T
FO
R
C
_
B
I
A
S
TH
_FA
U
LT
R
E
SET
B
LO
P
W
R
NC
V
SS5
T r i p a t h T e c h n o l o g y, I n c . - T e c h n i c a l I n f o r m a t i o n
2
TLD4012 JB/Rev. 2.0a/05.02
O V E R V I E W
TLD4012 is a low-power, low-distortion ADSL line driver. This driver offers power consumption ranging
from 600mW to 650mW, and provides active, or synthetic, output impedance matching to reduce power
consumption. This driver supports an impedance synthesis factor of 2.55 (refer to Figure 1 in the
"Test/Applications Circuits" section of this document). The table below summarizes the total power
consumption of this device for FDM and overlapped transmissions. Power consumption is reduced by
using +/-14V supplies for VDD15/VSS15.
High supplies
VDD15/VSS15
Power consumption FDM
(non-overlapped)
(19.8dBm)
Power consumption
overlapped
(20.4dBm)
+/- 14.0 V
650 mW
710 mW
+/- 15.0 V
675 mW
740 mW
Power consumption values given above, and in the following specifications, are for total power consumed
from the supplies. This includes power dissipated in the device and power delivered to the load, where the
load includes both the line and the matching resistors. Power dissipation in the driver can be determined
by subtracting power delivered to the load (line and matching resistors) from the power consumption given
in the specifications. The power consumption provided above does not account for loading due to the
hybrid which will vary with application.
With +/-14V supplies, the maximum output swing, V
OUTMAX
, is at least 40
VPPDIFF
over process, temperature
and a 5% supply tolerance. This is sufficient for full-power FDM signals with a PAR of 6.45. Note that
when using +/-14V supplies with a 5% tolerance the worst-case spurious free dynamic range in the
receiving band, and intermodulation distortion may be degraded slightly from the values given in the
specifications below. When using 14V nominal supplies the maximum degradation expected when the +/-
14V supplies are 5% low (minimum +/-13.3V) versus +/-15V supplies 5% low (minimum +/-14.25V) is less
than 4dB worse case.
All other minimum and maximum specifications in the tables that follow are valid from +/-13.3 to +/-15.75V
on VSS15/VDD15. This allows the use of +/-14V supplies with a 5% tolerance for VSS15/VDD15.
Lower PAR (peak-to-average ratio) values allow the high voltage supplies (VSS15 and VDD15) to be
reduced further, thus reducing power consumption. For example, for a 5.3 PAR VSS15/VDD15 can be
reduced to +/-12V. This will reduce power consumption to about 600mW for full-rate, 19.8dBm ADSL
FDM (non-overlapped) transmissions. Contact Tripath regarding use of the TLD4012 below +/-13.3V.
The recommended values for the line-matching resistors, R
S
, and the recommended transformer turns
ratios to properly match the line are (see Figure 1 in "Test/Application" section below):
R
S
= 10
N = 1:1.4
The 2.55 synthesis factor of the TLD4012 and the values above for R
S
and N
will result in a match to the
100
line impedance. The synthesis factor, k, is defined as the factor by which the line driver multiplies the
line-matching resistor, R
S
.
If your application can take advantage of higher synthesis factors, contact Tripath regarding options that
can reduce power consumption still further.
T r i p a t h T e c h n o l o g y, I n c . - T e c h n i c a l I n f o r m a t i o n
3
TLD4012 JB/Rev. 2.0a/05.02
A B S O L U T E M A X I M U M R A T I N G S
SYMBOL PARAMETER
Value
UNITS
V
DD5
Positive 5V Supply Voltage
+ 6
V
V
SS5
Negative 5V Supply Voltage
- 6
V
V
DD15
Positive 15V Supply Voltage
+ 18
V
V
SS15
Negative 15V Supply Voltage
- 18
V
T
J
Maximum Junction Temperature
150
C
T
A
Operating Free-air Temperature Range
-40 to +85
C
T
STORE
Storage Temperature Range
-55 to 150
C
T
SOLDER
Manual soldering for three seconds
Reflow soldering for five seconds
350
245
C
I
OUT
Output current limit, OUTP or OUTN
1.1
A
V
IN
Input voltage, INP or INN
V
SS5
to V
DD5
V
V
CMR
Common mode input voltage range
V
SS5
to V
DD5
V
Notes:
1.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
2.
The absolute value of VDD5 and VSS5 must always be less than or equal to the absolute value of VDD15 and
VSS15.
3.
The TLD4012 incorporates an exposed die pad on the underside of its package. This acts as a heat sink
and must be connected to a copper plane on the printed circuit board for proper heat dissipation.
Failure to do so may result in exceeding the maximum junction temperature which could permanently
damage the device. This copper plane must be connected to VSS15. See the Application Information
section of this document for additional information.
4.
Application must insure that VSS15 is applied before VSS5. A clamp diode connected between VSS5 and
VSS15 can be used to insure proper application of supply voltages to the TLD4012 (see Test/Application
Circuits of this document). Note that only one diode is needed per board for multi-channel line cards, but diode
selection should account for the increased current transient that the diode must carry for multiple channels. If
the +/-5V rail's rise time is fast, for example in applications in which the driver's supplies might be hot-plugged,
this method may not be sufficient and supply sequencing may be necessary.
R E C O M M E N D E D O P E R A T I N G C O N D I T I O N S
SYMBOL PARAMETER MIN.
TYP.
MAX.
UNITS
V
DD5
Positive 5V Supply Voltage
+ 4.75
+ 5
+ 5.25
V
V
SS5
Negative 5V Supply Voltage
- 5.25
- 5
- 4.75
V
V
DD15
Positive 15V Supply Voltage
+ 13.3
+ 15 + 15.75
V
V
SS15
Negative 15V Supply Voltage
- 15.75
- 15
- 13.3
V
V
IH
High-level Input Voltage, all digital inputs
2.7
+V
DD5
V
V
IL
Low-level Input Voltage, all digital inputs
0
0.8
V
I
ODLEAK
Open drain leakage current, FAULT output
1
A
I
ODMAX
Open drain sink current at V
OL
=0.4V max, FAULT output
1
mA
Note: Recommended Operating Conditions indicate conditions for which the device is functional. See Electrical
Characteristics for guaranteed specific performance limits.
T r i p a t h T e c h n o l o g y, I n c . - T e c h n i c a l I n f o r m a t i o n
4
TLD4012 JB/Rev. 2.0a/05.02
E L E C T R I C A L C H A R A C T E R I S T I C S
Unless otherwise specified, T
A
= 25
C, VDD5 = +5V, VSS5 = -5V, VDD15 = +15V, VSS15 = -15V. Also, see
Test/Application Circuits. See functional description for details regarding synthetic output impedance. Minimum and
maximum limits are guaranteed but may not be 100% tested.
SYMBOL PARAMETER
CONDITIONS MIN.
TYP.
MAX.
UNITS
P
CONS1
Power Consumption
R
LOAD
= 71
, P
OUT
= 154 mW,
Full-rate, overlapped ADSL signal, line
power = 110 mW (20.4 dBm), with
synthetic output impedance
(see Fig. 1)
740 mW
P
CONS3
Power Consumption, no signal
R
LOAD
= 50
, No Input Signal,
LOPWR = Low (see Fig. 1)
250 mW
P
CONS4
Power Consumption, no signal, low power
mode
R
LOAD
= 50
, No Input Signal,
LOPWR = High (see Fig. 1)
130 mW
P
CONS5
G.Lite
R
LOAD
= 71
, P
OUT
= 58 mW,
G.Lite signal, line power = 41.6 mW
(16.2 dBm). See Fig. 1.
390 mW
P
CONS6
Disable mode
RESETB = Low
10
mW
I
DD5
Operating Current VDD5
R
LOAD
= 71
, P
OUT
= 154 mW,
Full-rate, overlapped ADSL signal with
synthetic output impedance
(see Fig. 1)
47.0 mA
I
SS5
Operating Current VSS5
R
LOAD
= 71
, P
OUT
= 154 mW,
Full-rate, overlapped ADSL signal with
synthetic output impedance
(see Fig. 1)
49.0 mA
I
DD15
Operating Current VDD15
R
LOAD
= 71
, P
OUT
= 154 mW,
Full-rate, overlapped ADSL signal with
synthetic output impedance
(see Fig. 1)
8.0 mA
I
SS15
Operating Current VSS15
R
LOAD
= 71
, P
OUT
= 154 mW,
Full-rate, overlapped ADSL signal with
synthetic output impedance
(see Fig. 1)
9.5 mA
I
q1
Quiescent Current (VDD5 and VSS5)
R
LOAD
= 71
, No input signal, LOPWR =
Low
21.7 mA
I
q2
Quiescent Current (VDD15 and VSS15) R
LOAD
= 71
, No input signal,
LOPWR = Low
1.1 mA
I
q1LP
Quiescent Current (VDD5 and VSS5), low
power mode
R
LOAD
= 71
, No input signal,
LOPWR = High
11.0 mA
I
q2LP
Quiescent Current (VDD15 and VSS15),
low power mode
R
LOAD
= 71
, No input signal,
LOPWR = High
0.68 mA
V
BG
Band-gap
Voltage
1.28 V
V
OUTmax
Differential Output Voltage, peak-to-peak
differential
Gain = 17.8 to 27.8 dB, R
LOAD
= 71
Gain = 12.8 to 16.8 dB, R
LOAD
= 71
42
20
V
I
OUTmax
Differential Output Current
R
LOAD
= 71
500 mA
I
SC
Short-circuit Output Current
R
EXT
= 24k
800 mA
V
IO
Differential Input Offset Voltage
600
V
V
OS
Offset Voltage Drift
30
V/C
V
OSHI
Differential Output Offset Voltage
Gain = 27.8dB, EN_AC = High, 5k
across INN and INP
-100 100 mV
I
b
Input Bias Current
EN_AC = Low
0.5
A
I
b
Differential Input Bias Current
0.2
A
R
IDIFF
Differential Input Resistance
800
k
C
IDIFF
Differential Input Capacitance
2
pF
R
OUTLP
Output Resistance (while in Low-power
mode)
LOPWR = High
0.5
T r i p a t h T e c h n o l o g y, I n c . - T e c h n i c a l I n f o r m a t i o n
5
TLD4012 JB/Rev. 2.0a/05.02
P E R F O R M A N C E C H A R A C T E R I S T I C S
Unless otherwise specified, T
A
= 25
C, VDD5 = +5V, VSS5 = -5V, VDD15 = +15V, VSS15 = -15V. Also,
see Test/Application Circuit. Minimum and maximum limits are guaranteed but may not be 100% tested.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNITS
BW
SS
Small-signal Bandwidth, -3 dB Gain = 20.8dB, V
OUT
= 1V
PPDIFF
10
MHz
SFDR
Spurious Free Dynamic Range
in the receive band with
respect to 40dBm ADSL
transmit signal
Gain = 20.8 dB, R
LINE
= 100
,
P
LINE
= 20.4 dBm,
f = 26 kHz to 138 kHz
-80 dB
IMD
Intermodulation Distortion
Gain = 22.8dB
10V
PPDIFF
each tone
f = 1.025MHz,
f = 50kHz
@ 50 kHz
@ 100 kHz
SFDR >1MHz
-84
-84
-75
dBc
HD2 2
nd
Harmonic Distortion
Gain = 17.8 to 27.8dB
R
LOAD
= 71
V
OUT
= 10V
PPDIFF
f = 100 kHz
f = 500 kHz
f = 1 MHz
-90
-77
-70
dBc
HD3 3
rd
Harmonic Distortion
Gain = 17.8 to 27.8dB
R
LOAD
= 71
V
OUT
= 10V
PPDIFF
f = 100 kHz
f = 500 kHz
f = 1 MHz
-83
-82
-63
dBc
HD5 5
th
Harmonic Distortion
Gain = 17.8 to 27.8dB
R
LOAD
= 71
V
OUT
= 10V
PPDIFF
f = 100 kHz
f = 500 kHz
f = 1 MHz
-93
-67
-55
dBc
SR
Slew Rate
VOUT from 10V to +10V, measured from
7.5V to +7.5V, Gain = 20.8 dB
200 V/s
e
N
Input Noise Voltage
Gain = 20.8dB, f = 10 KHz
8
nV/
Hz
i
N
Input Noise Current
Gain = 20.8dB, f = 10 kHz
2.9
pA/
Hz
e
NOTOT
Overall Output Noise Voltage Gain = 20.8dB, f = 30kHz to 1.1MHz,
R
IN
= 5k
188 nV/
Hz
CMRR
Common Mode Rejection
Ratio
Gain = 27.8 dB
V
IN
= 100 mV
PP
EN_AC = High
@ 100 kHz
@ 500 kHz
@ 1 MHz
65 83
70
65
dB
PSRR
VDD5
Power Supply Rejection Ratio,
VDD5
Gain = 22.8 dB
V
SUPPLYAC
= 100 mV
PP
@ 100 kHz
@ 500 kHz
@ 1 MHz
70
60
50
dB
PSRR
VSS5
Power Supply Rejection Ratio,
VSS5
Gain = 22.8 dB
V
SUPPLYAC
= 100 mV
PP
@ 100 kHz
@ 500 kHz
@ 1 MHz
60
52
45
dB
PSRR
VDD15
Power Supply Rejection Ratio,
VDD15
Gain = 22.8 dB
V
SUPPYAC
= 100 mV
PP
@ 100 kHz
@ 500 kHz
@ 1 MHz
82
76
67
dB
PSRR
VSS15
Power Supply Rejection Ratio,
VSS15
Gain = 22.8 dB
V
SUPPLYAC
= 100 mV
PP
@ 100 kHz
@ 500 kHz
@ 1 MHz
75
59
51
dB
Gain
Gain accuracy
Output=TBDV
PPDIFF
, 500kHz
-0.4
0.4
dB
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