Microsoft PowerPoint - TGA4953EPU_Datasheet_2003_06_10
TriQuint Semiconductor Texas : (972)994 8465 Fax (972)994 8504 Web: www.triquint.com
Advance Product Datasheet
1
9.9-11.2Gb/s Optical Modulator Driver TGA4953-EPU
OC-192 Metro and Long Haul Applications
Surface Mount Package
Key Features and Performance
Metro MSA Compatible
Wide Drive Range (3V to 10V)
Single-ended Input / Output
Low Power Dissipation (1W at Vo=6V)
Very Low Rail Ripple
25 ps Edge Rates (20/80)
Small Form Factor
- 11.4 x 8.9 x 2 mm
- 0.450 x 0.350 x 0.080 inches
Evaluation Board Available.
Primary Applications
Mach-Zehnder Modulator Driver for
Metro and Long Haul.
Description
The TriQuint TGA4953-EPU is part of a series of surface
mount modulator drivers suitable for a variety of driver
applications and is compatible with Metro MSA standards.
The 4953 consists of two high performance wideband
amplifiers combined with off chip circuitry assembled in a
surface mount package. A single 4953 placed between
the MUX and Optical Modulator provides OEMs with a
board level modulator driver surface mount solution.
The 4953 provides Metro and Long Haul designers with
system critical features such as: low power dissipation
(1.1 W at Vo=6 V), very low rail ripple, high voltage drive
capability at 5V bias (6 V amplitude adjustable to 3 V), low
output jitter (10 ps typical), and low input drive sensitivity
(250 mV at Vo=6 V).
The 4953 requires external DC blocks, a low frequency
choke, and control circuitry.
The TGA4953-EPU is available on an evaluation board.
June 10, 2003
Note: Devices designated as EPU are typically early in their characterization process prior to finalizing all electrical and process
specifications. Specifications are subject to change without notice.
TGA4953 Evaluation Board (Metro MSA Conditions)
10.7 Gb/s, Vplus=5 V, Id=210 mA, (Pdc=1.1 Watt)
Vout=6 Vpp, CPC=50%, Vin = 500 mVpp
Scale: 2 V/div, 15 ps/div
Measured Performance
TriQuint Semiconductor Texas : (972)994 8465 Fax (972)994 8504 Web: www.triquint.com
Advance Product Datasheet
2
SYMBOL
PARAMETER 6/
VALUE
NOTES
Vd1, Vd2T
POSITIVE SUPPLY VOLTAGE
Drain Voltage
8 V
Id1
Id2T
POSITIVE SUPPLY CURRENT
Drain Current
Drain Current
100 mA
300mA
1/
P
d
POWER DISSIPATION
4 W
2/
Vg1, Vg2
Ig1, Ig2
NEGATIVE GATE
Voltage
Gate Current
0 V to 3 V
5 mA
Vctrl1, Vctrl2
Ictrl1, Ictrl2
CONTROL GATE
Voltage
Gate Current
Vd/2 to 3 V
5 mA
3/
P
IN
V
IN
RF INPUT
Sinusoidal Continuous Wave Power
10.7Gb/s PRBS Input Voltage Peak to Peak
23 dBm
4 Vpp
T
CH
OPERATING CHANNEL TEMPERATURE
150
0
C
4/ 5/
T
STG
STORAGE TEMPERATURE
-40 to 125
0
C
TGA4953EPU
Notes:
1/ Assure the combination of Vd and Id does not exceed maximum power dissipation rating.
2/ When operated at this bias condition with a base plate temperature of 80
0
C, the median life is reduced.
3/ Assure Vctl1 never exceeds Vd1 and assure Vctrl2 never exceeds Vd2 during bias up and down sequences.
4/ These ratings apply to each individual FET.
5/ Junction operating temperature will directly affect the device median time to failure (MTTF). For maximum
life, it is recommended that junction temperatures be maintained at the lowest possible levels.
6/ These ratings represent the maximum operable values for the device.
MAXIMUM RATINGS
Note: Devices designated as EPU are typically early in their characterization process prior to finalizing all electrical and process
specifications. Specifications are subject to change without notice.
TriQuint Semiconductor Texas : (972)994 8465 Fax (972)994 8504 Web: www.triquint.com
Advance Product Datasheet
3
Parameter
Test Condition
P
diss
(W)
T
Base
(
C)
T
CH
(
C)
R
JC
(
C/W)
MTTF
(HRS)
R
JC
Thermal Resistance
(channel to backside of
carrier)
Vd2T=4.7V,
Id2T=150mA +/-5%
.71
80
98
26
>1E6
THERMAL INFORMATION
Notes:
1. Based on a detailed thermal model of the output stage where channel temperature is highest.
Assumes worst case power dissipation condition (where no RF is applied at the input (no
power is dissipated in the load).
2. Thermal transfer is conducted thru the bottom of the TGA4953EPU package into the motherboard.
Design the motherboard to assure adequate thermal transfer to the base plate.
TGA4953EPU
Note: Devices designated as EPU are typically early in their characterization process prior to finalizing all electrical and process
specifications. Specifications are subject to change without notice.
TriQuint Semiconductor Texas : (972)994 8465 Fax (972)994 8504 Web: www.triquint.com
Advance Product Datasheet
4
RF SPECIFICATIONS
(T
A
= 25
C Nominal)
NOTE
TEST
MEASUREMENT
CONDITIONS
VALUE
UNITS
MIN
TYP
MAX
SMALL SIGNAL BW
8
GHz
SATURATED POWER BW
12
GHz
1/, 2/
SMALL-SIGNAL
GAIN MAGNITUDE
2 and 4 GHz
6 GHz
10 GHz
14 GHz
18 GHz
30
28
26
19
12
dB
GAIN FLATNESS
500KHz thru 5GHz
+/-1
dB
SMALL SIGNAL AGC RANGE
Midband
30
dB
NOISE FIGURE
3 GHz
2.5
dB
3/, 4/
EYE AMPLITUDE
VD2T=8.0V
VD2T=6.5V
VD2T=5.5V
VD2T=4.5V
VD2T=4.0V
10
8.0
7.0
6.0
5.5
Vpp
5/
ADDITIVE JITTER (rms)
.5
ps
6/, 7/
SATURATED OUTPUT
POWER
2, 4, 6, 8, and
10 GHz
25
dBm
1/, 2/
INPUT RETURN LOSS
MAGNITUDE
2, 4, 6, 10, 14, and
18GHz
10
15
dB
1/, 2/
OUTPUT RETURN LOSS
MAGNITUDE
2, 4, 6, 10, 14, and
18GHz
10
15
dB
RISE TIME (20/80)
25
30
ps
TGA4953EPU
Note: Devices designated as EPU are typically early in their characterization process prior to finalizing all electrical and process
specifications. Specifications are subject to change without notice.
TriQuint Semiconductor Texas : (972)994 8465 Fax (972)994 8504 Web: www.triquint.com
Advance Product Datasheet
5
Notes:
1/ Verified at package level RF test.
2/ Package RF Test Bias: Vd=5 V, adjust Vg1 to achieve Id=65 mA then adjust Vg2 to achieve
Id=200mA, Vctrl=+0.2 V
3/ Verified by design, SMT assembled onto a demonstration board detailed on sheet 6.
4/ Vin=250mV, Data Rate = 10.7Gb/s, VD1=VD2T or greater, VCTRL2 and VG2 are adjusted for maximum output.
5/ Computed using RSS Method where Jrms_additive = SQRT(Jrms_out
2
- Jrms_in
2
)
6/ Verified at die level on-wafer probe.
7/ Power Bias Die Probe: Vtee=8 V, adjust Vg to achieve Id=175 mA+/-5%, Vctrl=1.5 V
Note: At the die level, drain bias is applied thru the RF output port using a bias tee, voltage
is at the DC input to the bias tee.
TGA4953EPU
Note: Devices designated as EPU are typically early in their characterization process prior to finalizing all electrical and process
specifications. Specifications are subject to change without notice.
RF SPECIFICATION
(Continued)
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