I Q

S E M I C O N D U C T O R , I N C .

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The TQ8105/TQ8106 are SONET/SDH transceivers that integrate

multiplexing, demultiplexing, SONET/SDH framing, clock-synthesis PLL, and

enhanced line and clock diagnostic functions into a single monolithic device.

The TQ8106 is a pin-compatible upgrade of the TQ8105 that includes a

Clock and Data Recovery (CDR) function. The TQ8105 and TQ8106 allow

maximum flexibility in the selection of internal/external Clock and Data

Recovery, Opto-Electronic (O/E) Module, and Reference Clock Sources.

On-chip PLLs use external RC-based loop filters to allow custom tailoring of
loop response and support the wide range of reference clock frequencies
found in SONET/SDH/ATM systems. For transmit clock synthesis or for CDR,
the PLLs exceed ANSI, Bellcore, and ITU jitter specifications for systems
when combined with industry-typical O/E devices such as Sumitomo, AT&T,
HP, and AMP. The TQ8105/TQ8106 PLLs provide byte clocks and constant-
rate 38.88 MHz and 51.84 MHz, synthesized clock outputs, providing
clocking for UTOPIA and other system busses. Transmit data may also be
clocked into the devices with respect to the reference clock.

Operating from a single +5V supply, the TQ8105/TQ8106 provides fully
compliant functionality and performance, utilizing direct-connected PECL
levels (differential or single-ended) for high-speed I/O. As compared to AC-
coupled schemes, the direct-coupled connections reduce jitter and
switching-level offsets due to data patterns. The TQ8105/TQ8106 can also
provide direct connection to high-speed I/O utilizing ECL levels with a 5V
supply. Low-speed bus, control, and clock I/O utilize TTL levels. (An ECL/
PECL reference clock input is also provided; at 155.52 MHz the input should
be only PECL/ECL.) Output TTL pins can be tristated and may also be
configured for V

with a 3.3V supply connection.

TQ8105/8106

SONET/SDH

Overhead

Processor

TQ8105

TQ8106

SONET/SDH
Transceiver

Tx O/E

Rx O/E

with

CDR

SONET/SDH

Overhead

Processor

TQ8106

SONET/SDH
Transceiver

with CDR

Tx O/E

Rx O/E

Reference

Clock

SONET/SDH
Transceivers

Features

· Single-chip, byte-wide Mux,

Demux, Framer, and Tx clock-
synthesis PLL with enhanced
diagnostics

· TQ8106 includes monolithic

Clock and Data Recovery

· SONET/SDH/ATM compliant for

STS-12/STM-4 (622 Mb/s) or
STS-3/STM-1 (155 Mb/s) rates

· 155.52, 77.76, 51.84, 38.88, or

19.44 MHz reference clock inputs
with TTL, PECL, or ECL level

· 38.88 MHz and 51.84 MHz clock

outputs for UTOPIA as well as
byte clock rate (77.76 or 19.44 MHz)

· External RC-based loop filters

· Integrated loopbacks with

enhanced line and reference
clock diagnostics

· Direct-coupled standard, PECL,

high-speed I/O with ECL option

· Clean TTL interface to

PMC-Sierra devices

· 100-pin 14x14 mm JEDEC

plastic package

· +5V-only supply for PECL I/O

(5.2V required for ECL I/O option)

· 40 to +125

C case operating

temperature

TQ8105/TQ8106

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Figure 1. TQ8105 Block Diagram

The combination of a thermally enhanced, 100-pin

JEDEC, metric, plastic package, the low-power

dissipation of the device, and the wide case-

temperature range permits operation without a heat

sink in most designs.

The TQ8106 uses the same pinout as the TQ8105 and

is compatible with it.

The TQ8105/TQ8106 provides comprehensive,

integrated, loopback functionality and enhanced line

and reference clock diagnostics required of SONET/

SDH systems, minimizing additional external circuitry.

TQ8105/TQ8106 diagnostics include:

· Loss of Reference clock detector (LOR) output to

indicate that the PLL Reference Clock is not toggling

· Lock Indicator (RLOCK), which permits monitoring

of the receiver clock frequency, flagging when the
frequency drifts beyond approximately 500 ppm

· Loss of Signal (LOS) detector output to indicate that

the incoming data stream has no data transitions in
128-bit periods

· ECL/PECL input (NSOL) to allow LOS from an O/E

module to force the data stream to all zeroes,
eliminating the need for external glue logic.

CKSRC(2:0)

MXD(7:0)

TXD

TXCK

RXD

RXCK

ECL/

PECL

I/O

Block

DVPP

Parallel

Serial

DXD(7:0)

LBM(1:0)

PH(1:0)

Loop

Back &
Retime

Block

LOS

Detect

VPP

VNN

FP1

REFCKE

REFCKT

MMS

Clock

Data

Clock

Data

Clock

Data

Clock

Data

Ext. Clk

OC3

Hold

NOE

LOS

DXSYNC

OOF

Serial

Parallel

Clock

Phase

TxBC

RxBC

Framer

Clock/8

LOR

NRESET

SDHCK

PLL Clock

Synthesizer

FP2

NSOL

SONETC

CLRLOS

Freq.

Lock

Detect

RLOCK

FRPWR

TQ8105

TQ8105/TQ8106

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Figure 3. 100-Pin Enhanced Plastic 14x14 mm Package Pinout

Table 1. Signal Descriptions (continues on next page)

Pin

Signal

Function

Description

VNN

5.2V/Ground

ECL/PECL section power

No Connect

Do not connect

VPP

Ground/+5V

ECL/PECL Positive Supply (see Table 6B)

DVPP

Ground/+5V

ECL/PECL Driver Return (see Table 6B)

REFCKEN

ECL/PECL Input

Tx Ref. Clock or Bypass Clock, Complement

REFCKEP

ECL/PECL Input

Tx Ref. Clock or Bypass Clock, True

DVPP

Ground/+5V

ECL/PECL Driver Return (see Table 6B)

TXCKN

ECL/PECL Out

Transmit Clock, Complement

TXCKP

ECL/PECL Out

Transmit Clock, True

DVPP

Ground/+5V

ECL/PECL Driver Return (see Table 6B)

TXDN

ECL/PECL Out

Transmit Data, Complement

TXDP

ECL/PECL Out

Transmit Data, True

DVPP

Ground/+5V

ECL/PECL Driver Return (see Table 6B)

RXDN

ECL/PECL Input

Receive Data, Complement

RXDP

ECL/PECL Input

Receive Data, True

Note:

*TQ8106-specific signal

Note: *TQ8106-specific signal

TXDP

TXDN

DVPP

RXDP

DVPP

RXCKP

RXDN

DVPP

NSOL

VNN

GND

DVPP

RXCKN

DVPP

TXCKN

TXCKP

7
6

REFCKEP

VPP

REFCKEN

2
1

DXD2

DGND

DXD3

VCC

DXD1

DGND

DXD5

VCC

DXD4

VCC

DXD7

SVDD

VDD

DGND

DXD6

VCC

DXD0

DGND

DXSYNC

DGND

NC/CDRA

VDD*

VCC

RXBC

VDD

SVDD

VDD

LBM0

GND

NOE

GND

RLOCK

CLRLOS

CDRGND*/NC

LBM1

VCC

OOF

GND

LOS

DGND

MMS

OC3

NRESET

CKSRC2

CKSRC1

PH0

PH1

CKSRC0

VDD

SVDD

DGND

TXBC

VCC

SONETCK

VCC

MXD5

MXD4

MXD3

MXD6

MXD7

MXD0

MXD1

MXD2

LOR

DGND

SDHCK

AGND

FP2

VDD

FP1

REFCKT

100

GND

DVPP

NC/CDRFP2*
NC/CDRFP1*

VPP

GND

VNN

FRPWR

NCDREN*/NC

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Table 1. Signal Descriptions (continued)

Pin

Signal

Function

Description

DVPP

Ground/+5V

ECL/PECL Driver Return (see Table 6B)

RXCKP

ECL/PECL Input

Receive Clock, True (Ignored when CDR used)

RXCKN

ECL/PECL Input

Receive Clock, Complement (Ignored when CDR used)

DVPP

Ground/+5V

ECL/PECL Driver Return (see Table 6B)

VPP

Ground/+5V

ECL/PECL Positive Supply (see Table 6B)

NSOL

ECL/PECL Input

Loss of Signal -- zeroes serial data in when low; RXBC=TXCK/8

VNN

5.2V/Ground

ECL/PECL section power (see Table 6B)

NC/CDRFP1*

Analog Output

CDR Loop Filter Pin 1 -- Charge Pump Out (ignored by TQ8105)

NC/CDRFP2*

Analog Input

CDR Loop Filter Pin 2 -- VCO Tune (ignored by TQ8105)

GND

Core Ground

SVDD

+5V

Output Driver Internal Positive Supply

VDD

+5V

Core Positive Supply

CDRAVDD*

Analog +5V

TQ8106 CDR Analog +5V Supply
(not connected if CDR not used; ignored by TQ8105)

VCC

+5V/+3.3V

TTL Driver Positive Supply

RxBC

Tristate TTL Out

Demultiplexer Byte Clock

DGND

GND

TTL Driver Ground

DXSYNC

Tristate TTL Out

Frame Synchronization Signal

VCC

+5V/+3.3V

TTL Driver Positive Supply

DXD0

Tristate TTL Out

Demultiplexer Data Bit 0 (LSB)

DGND

GND

TTL Driver Ground

DXD1

Tristate TTL Out

Demultiplexer Data Bit 1

VCC

+5V/+3.3V

TTL Driver Positive Supply

DXD2

Tristate TTL Out

Demultiplexer Data Bit 2

DGND

GND

TTL Driver Ground

DXD3

Tristate TTL Out

Demultiplexer Data Bit 3

VCC

+5V/+3.3V

TTL Driver Positive Supply

DXD4

Tristate TTL Out

Demultiplexer Data Bit 4

DGND

GND

TTL Driver Ground

DXD5

Tristate TTL Out

Demultiplexer Data Bit 5

VCC

+5V/+3.3V

TTL Driver Positive Supply

DXD6

Tristate TTL Out

Demultiplexer Data Bit 6

DGND

GND

TTL Driver Ground

DXD7

Tristate TTL Out

Demultiplexer Data Bit 7 (MSB)

SVDD

+5V

Output Driver Internal Positive Supply

VDD

+5V

Core Positive Supply

NC/CDRGND*

GND

GND for TQ8106 to powerup CDR (ignored by TQ8105)

GND

Core Ground

FRPWR

TTL Input

Framer Power Control (power on when high)

OOF

TTL Input

Out-of-Frame: Initiates Frame Search/Bit Alignment

VCC

+5V/+3.3V

TTL Driver Positive Supply

LOS

Tristate TTL Output

Loss of Signal (high when > 128 bit periods without transitions)

DGND

GND

TTL Driver Ground

Note:

*TQ8106-specific signal

TQ8105/TQ8106

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Table 1. Signal Descriptions (continued)

Pin

Signal

Function

Description

CLRLOS

TTL Input

Active-high Clear LOS output

RLOCK

Tristate TTL Output

Receive Clock meets lock criteria when high

LBM1

TTL Input

Loopback Mode Control (see Table 3)

GND

Core Ground

LBM0

TTL Input

Loopback Mode Control (see Table 3)

VDD

+5V

Core Positive Supply

NOE

TTL Input

TTL tristate control (active low to enable)

GND

Core Ground

NRESET

TTL Input

Global Reset (active low)

OC3

TTL Input

OC3/OC12 Mode Select

MMS

TTL Input

Master/Slave Mode Control

CKSRC2

TTL Input

Clock Source Select (see Table 3)

CKSRC1

TTL Input

Clock Source Select (see Table 3)

CKSRC0

TTL Input

Clock Source Select (see Table 3)

PH1

TTL Input

TxBC Phase Select (see Table 3)

PH0

TTL Input

TxBC Phase Select (see Table 3)

VDD

+5V

Core Positive Supply

SVDD

+5V

Output Driver Internal Positive Supply

GND

Core Ground

MXD0

TTL Input

Multiplexer Data Bit 0 (LSB)

MXD1

TTL Input

Multiplexer Data Bit 1

MXD2

TTL Input

Multiplexer Data Bit 2

MXD3

TTL Input

Multiplexer Data Bit 3

MXD4

TTL Input

Multiplexer Data Bit 4

MXD5

TTL Input

Multiplexer Data Bit 5

MXD6

TTL Input

Multiplexer Data Bit 6

MXD7

TTL Input

Multiplexer Data Bit 7 (MSB)

VCC

+5V/+3.3V

TTL Driver Positive Supply

TxBC

Tristate TTL Out

Transmit Byte Clock

DGND

GND

TTL Driver Ground

SONETCK

Tristate TTL Out

51.84 MHz Clock Output

VCC

+5V/+3.3V

TTL Driver Positive Supply

SDHCK

Tristate TTL Out

38.88 MHz Clock Output

DGND

GND

TTL Driver Ground

LOR

Tristate TTL Out

Indicates Reference Clock is Absent

AGND

Analog Ground

VCO Analog Ground

FP2

Analog Output

Transmit PLL Loop Filter, Charge Pump Out

FP1

Analog Input

Transmit PLL Loop Filter, VCO Tune

AVDD

Analog +5V

VCO & Filter Analog VDD Supply

VDD

+5V

Core Positive Supply

REFCKT

TTL Input

Tx Reference Clock or Bypass Clock

GND

Core Ground

100

NC/NCDREN*

TTL Input

Internal Pull-up, Low = CDR receiver clock; Float = Pin 17/18 Rx Clk
(ignored by TQ8105)

Note:*TQ8106-specific signal

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Function Description

PLL

The TQ8105 & TQ8106 incorporate high-stability, low-
jitter Phase Locked Loops (PLLs) running at 2488.32
MHz. The PLLs use external surface mounted loop filters
consisting of an RC network as shown in the diagrams
that accompany the values shown in Table 2. Analog
design principles should be applied to the loop filter
portions of the circuit to ensure optimal jitter generation
performance. To reduce cross-coupling of clocks, both
CDR clocks and analog pins should be isolated from the
transmit PLL clock and analog pins. An analog ground
plane under the two capacitors and the resistor, along
with guards around the filter pins is excellent practice, as
is a well-filtered analog supply (AVDD) and a clean
analog ground (AGND). The loop filter values specified in
this preliminary data sheet may change.

Reference clock sourcing can be through a variety of
mechanisms. As shown in Table 3, the MMS pin
determines whether the device operates in Master
mode (where the PLL reference comes in on either a
TTL or PECL/ECL pin), or a Slave mode (where the PLL
reference is derived from the DEMUX high-speed line
clock input). If the external reference clock pins are
used, note that they are logical ORs and that the
unused pin should be tied to (a) GND for unused
REFCKT, or (b) REFCKEN should be tied to VPP for TTL
reference operation. The reference clock frequency can
be selected from any number of values, as indicated in
Table 3. Note that the PLL may be bypassed, allowing
use of an external clock reference.

Internal dividers determine the operating line rate, as
shown in Table 3. The device is capable of operating at
STM1/STS-3 or STM4/STS-12 rates. The transmit PLL
provides high performance and compliance with ITU/
Bellcore requirements found in the first-generation
TQ8101. The TQ8106 receiver's CDR can be disabled
for backwards pin-compatibility with the TQ8105. For
circuits not requiring the TQ8106's CDR, the CDR is
disabled by floating NCDREN (pin 100). Further, the CDR

section of the TQ8106 can be powered down by
disconnecting the CDRGND and CDRAVDD pins, thereby
reducing power consumption. If the TQ8106 CDR is not
used, the CDR filter pins may be left unconnected.

The transmit PLL also provides constant-rate 38.88 MHz
and 51.84 MHz TTL outputs which may be tristated. The
38.88 MHz & 51.84 MHz output may also be achieved by
using high-speed receiver timing in Clock Source Mode
011 (see Table 3).

Framer

The TQ8105 and TQ8106 provide a clean interface to
devices from PMC-Sierra and others. The Out-of-Frame
(OOF) input is a state (level)-initiated event, rather than
the edge-triggered event found on TriQuint's first-
generation TQ8101 transceiver. When OOF is high, the
TQ8105/TQ8106 initiates a frame search for a serial bit
pattern of twelve A1s (three A1s in OC3 mode) followed
by three A2s. If a match occurs, the device realigns
byte boundaries and issues a logic high on the DXSYNC
pin during the third A2. In the absence of OOF, the
device will not realign byte boundaries, but will report
any bit-level matching of twelve A1s (three A1s in OC3
mode) followed by three A2s as a DXSYNC pulse.

Framer circuit power may be switched off by a TTL low on
the FRPWR pin, saving approximately 0.25W. No further
DXSYNC pulses will be issued, though bit alignment is
preserved in the demux. Note that the OOF and FRPWR
pins may be tied together, powering the framer only when
bit realignment is required (this is not recommended
practice, however, due to the inrush currents that may
result).

Loopbacks

As part of the TQ8105 and TQ8106 on-chip diagnostics,
four loopback modes are supported. These are selected
by the dedicated pins LBM0 and LBM1, as shown in
Table 3. The loopback modes are shown in Figure 5.

TQ8105/TQ8106

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Functional Description (continued)

Enhanced Diagnostics

The TQ8105 and TQ8106 incorporate on-chip clock
diagnostics, allowing fast, efficient fault detection and
isolation at the systems level.

The LOR (Loss Of Reference) output goes high when the
reference clock is absent. Note that this signal is not
latched and is only high when the reference clock is
missing. A reference clock is required for the TQ8106
CDR to function correctly.

The NSOL (Loss-of-signal input, active low, PECL/ECL
level) input allows the receiver to force zeroes onto the
demux outputs. A TTL-level signal may also be used for
NSOL if the resistor network, shown in the applications
section of this data sheet, is used. NSOL is useful when a
Loss Of Signal occurs on the receive optics, and a
quieting of invalid data is desired. The receiver is clocked
from the transmit clock when NSOL is active, and the
output RXBC clock is obtained from the transmit portion
of the TQ8105/TQ8106. This ensures compatibility with
devices, such as the PMC-Sierra S/UNI-622 and STTX
components, which may contain dynamic registers that
lose contents if clocks are removed. NSOL forces the
CDR to lock on REFCLK, except when in slave mode.

The LOS (Loss Of Signal) output goes high whenever
128-bit periods occur without transitions on the data
input to the demux. CLRLOS forces LOS low.

The RLOCK (Receiver LOCK) output goes low whenever the
signal on RXCK or the recovered clock drifts more than
500 ppm from the reference frequency. This output returns
high whenever the frequency accuracy is within 100 ppm.

Demux

The TQ8105/TQ8106 demultiplexer converts an NRZ
PECL/ECL data input, at either 155 Mb/s or 622 Mb/s,
and its corresponding PECL/ECL clock into a byte-parallel

78 MHz or 19 MHz tristatable TTL data bus. The timing is
shown in Figures 6 through 8. See the previous "Framer"
description for bit alignment details. The TQ8106 can
recover both clock and data from a NRZ data stream,
whereas the TQ8105 requires NRZ data and a recovered
clock.

Mux

The TQ8105/TQ8106 multiplexer converts a 78 MHz or
19 MHz byte-wide bus to a serial NRZ PECL/ECL data
stream. The bytes are clocked into the device with the
TXBC byte clock output. The timing is shown in Figures
6 through 8. Note that the TXBC output can be adjusted
in 90-degree phase increments to accommodate
variations in interface requirements. See Table 3 for
settings on the PH0 and PH1 pins controlling this
function. Data may also be clocked into the TQ8105/
TQ8106 by a 77 MHz reference, oscillator-clock source,
provided the data is within the timing limits shown in the
timing diagram labelled "Reference Clock Based
Transmit Timing." The TQ8105 and TQ8106 do not
require the transmit latch found on earlier TQ8101
reference designs and are backwards compatible with
designs that have the latch incorporated.

High-Speed I/O and TTL Interfaces

The TQ8105/06P will operate with either PECL or ECL
operation on the high-speed I/O. With a single +5V
supply, the part interfaces directly with TTL and PECL
(Positive Emitter Coupled Logic). By providing an
additional -5.2V supply, the device's high-speed I/O
becomes ECL, instead of PECL. The TQ8105/06S is
designed only for PECL high-speed I/0 operation with a
single +5V supply. The power supply connections for
PECL and ECL are shown in Table 6B.

The TTL outputs (Vcc) may be connected to either +5V or
+3.3V supplies. True TTL may be obtained with the +5V
connection; clamped operation, when connected to +3.3V,
ensures that maximum Voh levels do not exceed +3.3V.

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PRODUCTS

TQ8105/TQ8106 Design Notes

These design notes are provided to assist the circuit

designer in achieving the highest possible performance

while reducing design time. Unless noted otherwise,

references to the TQ8105 apply equally to the TQ8106.

Interfacing to PMC-Sierra Devices

The transmit timing of the TQ8105 is such that the
PMC-Sierra byte outputs (POUT(0:7)) may be directly
connected to the TQ8105 mux inputs (MXD(0:7)). The
TQ8105 uses an Out-Of-Frame (OOF) input as a signal
to reframe while high, allowing direct connection of the
PM5355's OOF output to the TQ8105 OOF input. The
following summarizes connectivity between the devices.

PM5355

TQ8105/TQ8106

POUT(0:7)

MXD(0:7)

PIN(0:7)

DXD(0:7)

OOF

PICLK

RXBC

FPIN

DXSYNC

TCLK

TXBC

POP(0:5)

Any TQ8105 modes to be programmable

PIP(0:3)

Any TQ8105 diag outputs to be readable

Reference Design

A reference design (see Figure 4) and evaluation board
are available from TriQuint. They incorporate a 1x9 or
2x9 fiber optic transceiver (with the option of clock
recovery), the PM5355 PMC Sierra framer device, and
a TQ8105 or TQ8106.

Thermal Considerations

Figure 9 shows the region where the use of a heatsink is
not required. For example, the TQ8105 does not require
a heatsink for ambient temperatures up to 55

C in still

air. An airflow of 100 LFPM raised this temperature to
approximately 75

C, eliminating heatsink requirements.

In applications requiring a heatsink, a standard pin-fin
heat-sink is appropriate. To attach the sink, use spring

clips soldered to the board to cross and hold the
heatsink. The clip holes in the board are at the corners of
a 1.275" x 1.5" rectangle. Another alternative is the
circular heatsink, #2288B from Thermalloy attached with
their Thermattach #19686-3.

Power Supplies

Good decoupling practices should be observed, with a
0.1 uF decoupling capacitor at each supply pin, ideally
on the component side of the board. Keep the analog
supplies (Vdd and AVdd) pristine. Proper design will
isolate the supply groups using point grounding to tie
supplies together (

all

grounds at a single point having

multiple vias).

For the analog supply, flood copper under the loop filter
on the component side of the board, tying the flood to
the analog ground pin, with the point ground away from
the filter and analog pin, so that any switching currents
are kept away from these areas. If any switching,
power-supply frequencies below 500 kHz are used in
the system, use a supply filter on the analog supply pin.
These practices help minimize the generation of jitter.

High-Speed Connections

Connections to E/O modules (and clock reference, if
used) are direct-coupled PECL and need to be terminated
with decoupled 50 ohms to 3V at the receiving end of the 50
ohm transmission line. Ensure that each 50 ohm resistor
(or Thevenin equivalent) has its own decoupling
capacitor. Place the resistor at the end of a 50 ohm
transmission line (use a controlled impedance layer),
ideally with a minimal-length stub attached to either the
resistor or the receiving device.

If there is no room for the resistor, use a minimal-
length stub to drop the signal at the receiving device
pins, continue the 50 ohm transmission line to an area
where the termination resistors can be placed, and
terminate at the endpoint of that line. If in doubt,
contact factory applications for assistance.

TQ8105/TQ8106

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0.1u

gnd_s

330

220

VDD

gnd_s

VDD

gnd_s

330

220

PIN0

148

PIN1

147

PIN2

146

PIN3

145

PIN4

144

PIN5

143

PIN6

142

PIN7

141

FPIN

149

FPOS

150

PICLK

137

TLAIS

TSD

103

TSOW

TSUC

TLRDI

TLD

TLOW

TTOH1

TTOH2

TTOH3

TTOH4

TTOHEN

101

TPOH

TPOHEN

TPAIS

TPRDI

RSICLK

139

RSIN

140

TSICLK

104

TFCLK

XOFF

TSOC

TXPRTY0

TXPRTY1

TWRENB

TDAT0

TDAT1

TDAT2

TDAT3

TDAT4

TDAT5

TDAT6

TDAT7

TDAT8

TDAT9

TDAT10

TDAT11

TDAT12

TDAT13

TDAT14

TDAT15

RRDENB

186

RFCLK

190

TSEN

192

TGFC

ALE

CSB

WRB

RDB

RSTB

TCK

TMS

126

TDI

127

TDO

TRSTB

125

FPOUT

123

POUT0

122

POUT1

121

POUT2

116

POUT3

115

POUT4

114

POUT5

113

POUT6

112

POUT7

111

OOF

164

LOF

163

LOS

169

TSDCLK

102

TOWCLK

RSDCLK

159

RSD

160

ROWCLK

168

RSOW

162

RSUC

161

OHFP

175

LAIS

171

LRDI

170

RLDCLK

173

RLD

172

RLOW

167

TLDCLK

RTOH1

156

RTOH2

155

RTOH3

154

RTOH4

153

RTOHCLK

157

RTOHFP

158

TTOHCLK

TTOHFP

100

RPOH

181

RPOHCLK

176

RPOHFP

177

TPOHCLK

TPOHFP

LOP

178

PAIS

182

PRDI

185

TSOUT

124

GTOCLK

GROCLK

174

LCD

188

RSOC

195

RXPRTY0

196

RXPRTY1

197

RDAT0

198

RDAT1

199

RDAT2

200

RDAT3

201

RDAT4

202

RDAT5

203

RDAT6

204

RDAT7

RDAT8

RDAT9

RDAT10

RDAT11

RDAT12

RDAT13

RDAT14

RDAT15

RCA

194

TCA

RCP

187

RGFC

193

TCP

POP0

135

POP1

134

POP2

133

POP3

132

POP4

131

POP5

130

PIP0

108

PIP1

107

PIP2

106

PIP3

105

INTB

S/UNI 622

VDD

gnd_s

VDD

77.76M Osc

gnd_s

0.1u

MXD0

MXD1

MXD2

MXD3

MXD4

MXD5

MXD6

MXD7

OOF

DXD0

DXD1

DXD2

DXD3

DXD4

DXD5

DXD6

DXD7

DXSYNC

RXBC

TXBC

REFCKT

REFCKEP

REFCKEN

RXDP

RXDN

RXCKP

RXCKN

NSOL

PH0

PH1

CKSRC0

CKSRC1

CKSRC2

LBM0

LBM1

MMS

OC3

CLRLOS

FRPWR

NOE

NRESET

LOR

FP1

FP2

AVDD

AGND

NCI_1

100

NCI_5

NCI_4

NCI_3

NCI_2

LOS

RLOCK

SDHCK

SONETCK

DVPP_1

DVPP_2

DVPP_3

DVPP_4

DVPP_5

DVPP_6

TXDP

TXDN

TXCKP

TXCKN

TQ8105

VDD

1uH

gnd_s

VDD

0.1u

10u

0.1u

VDD

gnd_s

REFCLK

LCKREFN

TDN

CLKN

CLK

RDN

HFBR5207

130

0.1u

gnd_s

VDD

*Note 1

130

UTOPIA

*Note 4

VDD

330

gnd_s

VDD

*Note 2

*330

gnd_s

*Note 3

330

VDD

gnd_s

VDD

4.7K

gnd_s

0.1u

10u

gnd_s

1uH

gnd_s

VDD

0.1u

VDD

1uH

0.1u

10u

0.1u

Note: See Tables 2A & 2B

for loop filter values.

gnd_s

VDD

20K

*Note 1

470

gnd_s

Notes:

1) Place termination networks as close to

their respective input pins as possible.

2) Setting of PH(0:1) is board-layout dependent.

These 4 resistors are used as placeholders

for the appropriate strapped settings that

are determined at initial board evaluation.

(See Table 3 and associated text.)

3) Install 0-ohm resistor for TQ8106 operation.

4) May use SONETCK (51.84MHz) for

UTOPIA bus clock.

gnd_s

VDD

NLOCKED

LOS

LOR

130

0.1u

130

gnd_s

10u

VDD

TQ8105 Decoupling

0.1u

gnd_s

(Decoupling not shown for PM5355)

*Only connections pertinent to the TQ8105/06

to S/UNI overhead processor chip are shown.*

10u

0.1u

10u

0.1u

VDD

0.1u

gnd_s

Reset

gnd_s

47u

gnd_s

10K

VDD

330

Figure 4. Reference Design Schematic

TQ8105/TQ8106

PRELIMINARY DATA SHEET

For additional information and latest specifications, see our website: www.triquint.com

Table 3. Mode Selection

Signals

Mode

LBM(1:0)

Loopback: 00 = Normal, 01 = Equipment, 10 = Facility, 11 = Split

PH(1:0)

00 = 0 degrees delay, 01 = 90 degrees delay, 10 = 180 degrees delay, 11 = 270 degrees delay

MMS

1 = Master (use REFCKT/E as reference), 0 = Slave (use receive clock as reference)

CKSRC(2:0)

Clock Source:

000 = PLL bypass

001 = 51.84 MHz PLL reference, SONETCK & SDHCK tristate

010 = 155.52 MHz PLL reference

011 = 51.84 MHz PLL reference, SONETCK=8, SDHCK derived from receiver timing

100 = 77.76 MHz PLL reference

101 = 51.84 MHz PLL reference

110 = 38.88 MHz PLL reference

111 = 19.44 MHz PLL reference

OOF

1 = Initiate frame search, 0 = Do not permit reframing (see FRPWR pin in Table 1)

NSOL

1 = Pass receive data, 0 = Force receive data to 0

OC3

1 = Operate at STM1/STS-3 (or PLL bypass divided by 4), 0 = Operate at STM4/STS-12/PLL bypass

NRESET

1 = Normal operation, 0 = Reset internal counters

NCDREN

1 = TQ8105/CDR Off mode, 0 = Enable CDR (TQ8106 only)

Table 4. Absolute Maximum Ratings

Parameter

Symbol

Level

Minimum

Maximum

Unit

Positive supply

CC,

, V

DD,

GND

Negative supply (V

= 0 V)

GND

Output voltage

ECL/PECL

0.5

+0.5

Output current

ECL/PECL

Input voltage

ECL/PECL

0.5

+0.5

Input current

ECL/PECL

Output voltage

TTL

0.5

+0.5

Output current

TTL

100

Input voltage

TTL

0.5

+0.5

Input current

TTL

Biased junction temperature

+150

Storage temperature

+150

TQ8105/TQ8106

PRODUCTS

PRELIMINARY DATA SHEET

For additional information and latest specifications, see our website: www.triquint.com

TELECOM

PRODUCTS

Table 6A. Recommended Operating Conditions

Parameter

Symbol

Minimum

Typical

Maximum

Unit

Positive supply

4.75

5.0

5.25

Output driver positive supply

3.0

5.25

Negative supply (ECL mode only)

5.5

5.2

4.75

Operating case temperature (see Figure 9)

125

Table 6B. Power Supply Connections

Pin

+5V TTL/PECL I/O

+3.3V TTL/PECL I/O

+5V TTL/ECL I/O

+3.3V TTL/ECL I/O

VDD

+5V

SVDD

+5V

VCC

+5V

+3.3V

+5V

+3.3V

AVDD

Filtered +5V

CDRAVDD

Filtered +5V

GND

0V (ground)

AGND

0V (ground)

CDRGND

0V (ground)

VPP/DVPP

+5V

0V (ground)

VNN

0V (ground)

-5.2V

Table 5. Power Consumption

Symbol

Function

Minimum

Typical

Maximum

Unit

+5V supply

0.323

TBD

+5V / +3V supply

0.016

TBD

+5V / 0V supply

0.055

TBD

ADD

+5V supply

0.018

TBD

Power dissipation, Framer on, TQ8106 CDR off

1.9

2.3

Power dissipation, Framer off, TQ8106 CDR off

1.7

2.1

Power dissipation, Framer on, TQ8106 CDR on

2.75

TQ8105/TQ8106

PRELIMINARY DATA SHEET

For additional information and latest specifications, see our website: www.triquint.com

Table 8. DC Characteristics--TTL I/O

(Specifications apply over recommended operating ranges)

Parameter

Condition

Symbol

Minimum

Nominal

Maximum

Unit

Input HIGH voltage

2.0

Input LOW voltage

0.8

Input HIGH current

IH(MAX)

200

Input LOW current

IL(MIN)

400

200

Output HIGH voltage

= 50 mA

2.4

Output LOW voltage

= 20 mA

0.4

Tristate current

100

Input capacitance

TBD

Output capacitance

OUT

TBD

ESD breakdown rating

(Design objective)

ESD

Class I

Table 7. DC Characteristics--ECL/PECL I/O

(Specifications apply over recommended operating ranges).

Parameter

Condition

Symbol

Minimum

Nominal

Maximum

Unit

Internal ECL reference

Single-ended inputs

REF

0.26 V

+ 0.74 V

Common mode voltage

Differential inputs

COM

1500

1100

Differential voltage

Differential inputs

DIFF

200

1200

Input HIGH voltage

REF

= 1300 mV

1050

400

Input LOW voltage

1550

Output HIGH voltage

LOAD

= 50 ohms

1000

600

to V

= V

2.0V

Output LOW voltage

LOAD

= 50 ohms

1600

to V

= V

2.0V

Input HIGH current

IH(MAX)

+130

335

Input LOW current

IL(MIN)

265

130

Output HIGH current

(Not tested; consistent

with V

and V

tests)

Output LOW current

(Not tested; consistent

with V

and V

tests)

Input capacitance

TBD

Output capacitance

OUT

TBD

ESD breakdown rating

(Design objective)

ESD

Class I

Note: V

= V

-2.0V

TQ8105/TQ8106

PRODUCTS

PRELIMINARY DATA SHEET

For additional information and latest specifications, see our website: www.triquint.com

TELECOM

PRODUCTS

Table 9. AC Characteristics

(Specifications apply over recommended operating ranges)

Parameter

Symbol

Minimum

Nominal

Maximum

Unit

RXCK clock period

C(RXCK)

1.6

REFCKE clock period

C(REFCKE)

1.6

TXCK clock period

C(TXCK)

1.6

REFCKT clock period

C(REFCKT)

12.8

TXBC clock period

C(TXBC)

12.8

RXBC clock period

C(RXBC)

12.8

REFCKT/REFCKE clock duty cycle

C(REF)

REFCKT to TXBC skew

2,3,5

SK(TXBC)

TBD

SONETCK clock period

C(SONETCK)

19.29

RXBC clock duty cycle

3,5

DC(RXBC)

TXBC clock duty cycle

3,5

DC(TXBC)

TXCK clock duty cycle

DC(TXCK)

SONETCK clock duty cycle

3,5

DC(SONETCK)

SDHCK clock duty cycle

3,5

DC(SDHCK)

RXCK clock duty cycle

DC(RXCK)

High-speed rise/fall time

(> 79 MHz), Data

H(R/F)

500

High-speed rise/fall time

(>79 MHz), Clock

H(R/F)

320

Low-speed rise/fall time

1,3,5

(< 79 MHz)

L(R/F)

RXD setup time to RXCK

(see Figure 6)

S(RXD)

240

RXD hold time to RXCK

(see Figure 6)

H(RXD)

OOF rising edge before A1 changes to A2

(OOFH)

51.44

(see Figure 8)

DXSYNC rising edge from parallel data output

(DSYNC)

25.72

change from A1 to A2

DXSYNC pulse width

3,5,7

(see Figure 8)

(DXSYNCPW)

11.0

RXBC falling edge to valid parallel data output

P(DXD)

0.5

1.0

(see Figure 7)

MXD(0:7) setup time to TXBC

2,3,5

(see Figure 6)

S(MXD)

600

MXD(0:7) hold time to TXBC

2,3,5

(see Figure 6)

H(MXD)

600

TXCK falling edge to TXD

(see Figure 7)

P(TXD)

200

400

220

330

18pF

Vcc

Notes: 1. At 0.8V/2.0V

levels

2. With PH(1:0) set to 00, 18pF total loading
3. TTL outputs test load (V

= +5V):

4. 20%/80%

levels

5. At 1.4V logic threshold level
6. Differential measurement
7. OC12 mode

TQ8105/TQ8106

PRODUCTS

PRELIMINARY DATA SHEET

For additional information and latest specifications, see our website: www.triquint.com

TELECOM

PRODUCTS

Ordering Information

TQ8105P

SONET/SDH Transceiver, PECL/ECL I/O

TQ8106P

SONET/SDH Transceiver w/CDR, PECL/ECL I/O

TQ8105S

SONET/SDH Transceiver, PECL I/O

TQ8106S

SONET/SDH Transceiver w/CDR, PECL I/O

Reference Designs

The following products are available for 14-day loan to qualified customers:

ATM SONET/SDH Line Interface Module (SLIM)

Supports OC12c/STM-4 (622.08 Mbps) and OC-3c/STM-1 (155.52 Mbps)

The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or
omissions. TriQuint assumes no responsibility for the use of this information, and all such information
shall be entirely at the user's own risk. Prices and specifications are subject to change without notice.
No patent rights or licenses to any of the circuits described herein are implied or granted to any third party.
TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems.

Revision 0.3.A

July 1998

Additional Information

For latest specifications, additional product information,

worldwide sales and distribution locations, and information about TriQuint:

Web: www.triquint.com

Tel: (503) 615-9000

Email: sales@tqs.com

Fax: (503) 615-8900

For technical questions and additional information on specific applications:

Email: applications@tqs.com

SLIM Documentation Package

· Functional Partition Drawing Set, including

block, state machine, and timing diagrams

· Schematics
· Programmable Logic Listings

· User's Manual / Product Specification

· PCB Artwork (all layers)

· Component Placement Drawing

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TQ8105

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TQ8105