Pre-Production Process
TQPED
0.5 um E/D pHEMT Foundry Service
Features
E-Mode, 0.35 V, Vth
D-Mode, -0.8 V Vp
InGaAs Active Layer pHEMT
Process
0.5 um Optical Lithography
Gates
High Density Interconnects:
2 Global
1 Local
High-Q Passives
Thin Film Resistors
High Value Capacitors
Backside Vias Optional
Based on Production TQPHT
pHEMT and Interconnect
Nominal TOM3 FET Models
Available
Applications
Highly Efficient, and Linear
Power Amplifiers
Low Loss, High Isolation, Low-
Harmonic Contnt Switches
Integrated digital control logic
for Switches and Transceivers
Converters
Integrated RF Front Ends LNA,
SW, PA
Wireless Transceivers, Base sta-
tions, Direct Broadcast Satellite
Radars, Digital Radios, RF /
Mixed Signal ICs
Power Detectors and Couplers
General Description
TriQuint's TQPED process is based on our production-released
0.5 m TQPHT process. TQPED partners an E-Mode pHEMT
device with our TQPHT D-Mode transistors to be the first
foundry pHEMT process to integrate E-Mode and D-Mode tran-
sistors on the same wafer. This process is targeted for low noise
amplifiers, linear, low loss and high isolation RF switch applica-
tions, converters and integrated RF Front Ends. The TQPED
process offers a D-Mode pHEMT with a 0.8 V pinch off, and an
E-Mode pHEMT with a +0.35 V threshold voltage. The three
metal interconnecting layers are encapsulated in a high perform-
ance dielectric that allows wiring flexibility, optimized die size
and plastic packaging simplicity. Precision NiCr resistors and
high value MIM capacitors are included allowing higher levels of
integration, while maintaining smaller, cost effective die sizes.
Page 1 of 3; Rev 1.0 12/1/2004
Isolation Implant
Pseudomorphic
Channel
N+
Metal 2 - 4um
Metal 1
Metal 2
Dielectric
Metal 1 - 2um
Dielectric
Dielectric
Metal 0
Nitride
Isolation Implant
Metal 1
MIM Metal
Isolation Implant
Pseudomorphic
Channel
N+
Metal 2 - 4um
Metal 1
Metal 2
Dielectric
Metal 1 - 2um
Dielectric
Dielectric
Metal 0
Nitride
Isolation Implant
Metal 1
MIM Metal
NiCr
E-Mode / D-Mode
pHEMT
NiCr Resistor
MIM Capacitor
Semi-Insulating GaAs Substrate
0.5 um pHEMT Device Cross-Section
Production Release: Q1'2005
Production Process
TQPED
0.5 um E/D pHEMT Foundry Service
Semiconductors for Communications
www.triquint.com
TriQuint Semiconductor
2300 NE Brookwood Pkwy
Hillsboro, Oregon 97124
Phone: 503-615-9000
Fax: 503-615-8905
Email: info@triquint.com
Page 2 of 5; Rev 2.0 7/22/03
Process Details @ Vds = 3.0V
Element
Parameter
Value
Units
D-Mode pHEMT
Vp (1uA/um)
-0.8
V
Idss
225
mA/mm
Imax
550
mA/mm
Breakdown, Vdg
15 min, 20 typ
V
Ft @ 50% Idss
25
GHz
Fmax @ 50% Idss
90
GHz
Gm (50% Idss)
350
mS/mm
Ron
1.5
Ohms * mm
E-Mode pHEMT
Vth (1uA/um)
+0.35
V
Idss
0.1
uA/um
Imax
310
mA/mm
Breakdown, Vdg
15 min, 18 typ
V
Ft @ 50% Idss
30
GHz
Fmax @ 50% Idss
100
GHz
Gm (50% Idss)
625
mS/mm
Ron
2.5
Ohms * mm
Common Process Element Details
Gate Length
0.5
m
Interconnect
3
Metal Layers
MIM Caps
Value
630
pF/mm2
Resistors
NiCr
50
Ohms/sq
Bulk
285
Ohms/sq
TQPED
Process
Details
Maximum
Ratings
Storage Temperature Range
-65 to +150
Deg C
Operating Temperature Range
-55 to +150
Deg C
EFET/DFET Transistor
(Vs open; Idg = 1uA/um)
15
V
Capacitor
40
V
Page 2 of 3; Rev 1.0 12/1/2004
Pre-Production Process
Design Tool Status
Complete Design Manual Now
Device Library of circuit elements: FETs, diodes, thin film
resistors, capacitors, inductors
Design Kit for Agilent's ADS design environment
Design Kit planned for AWR Microwave Office
Layout Library in GSD II format
Cadence Development Kit with PCells in Preliminary
Release
Layout Rule Sets for Design Rule Check for ICED, Ca-
dence
Qualified package models for supported package styles
Noise parameters on specific device sizes available
Please contact your local TriQuint Semiconductor Representative/ Distributor
or Foundry Services Division for Additional information:
E-mail: sales@triquint.com
Phone: (503) 615-9000
Fax: (503) 615-8905
Pre-Production Process
TQPED
0.5 um E/D pHEMT Foundry Service
TriQuint Semiconductor
2300 NE Brookwood Pkwy
Hillsboro, Oregon 97124
Phone: 503-615-9000
Fax: 503-615-8905
Email: info@triquint.com
Semiconductors for Communications
www.triquint.com
Page 3 of 3; Rev 1.0 12/1/2004
Prototyping and Development
Prototype Development Quick Turn (PDQ):
Shared mask set
Run monthly
Hot Lot cycle time
Prototype Wafer Option (PWO):
Customer-specific masks; Customer schedule
2 wafers delivered
Hot Lot cycle time
With thinning and sawing; optional backside vias
Process Qualification Status
Mature process based on TQPHT 150-mm process
Process release to production scheduled for Q1 2005
Full 150mm wafer Process Qualification in process. To
be completed early Q1 2005
For more information on Quality and Reliability, contact
TriQuint or visit: www.triquint.com/manufacturing/QR/
Applications Support Services
Tiling of GDSII stream files including PCM
Design Rule Check services
Layout Versus Schematic check services
Packaging Development Engineering
Test Development Engineering:
On-wafer
Packaged parts
Thermal Analysis Engineering
Yield Enhancement Engineering
Part Qualification Services
Failure Analysis
Training
GaAs Design Classes:
Half-Day Introduction; Upon request
Four-Day Technical Training; Fall and Spring at
TriQuint Oregon facility
For Training & PDQ Schedules, please visit:
www.triquint.com/foundry/
Manufacturing Services
Mask making
Production 150-mm wafer fab
Wafer Thinning
Wafer Sawing
Substrate Vias
DC Diesort Testing
RF On-wafer testing
Plastic Packaging
RF Packaged Part Testing
PDF 
ZIP