Production Process
TQPHT
0.5 um pHEMT Foundry Service
Features
D-Mode, -0.8 V Vp
InGaAs Active Layer pHEMT
Process
0.5 um Optical Lithography
Gates
17 V D-G Breakdown Voltage
High Density Interconnects:
2 Global
1 Local
High-Q Passives
Thin Film Resistors
High Value Capacitors
Backside Vias Optional
Based on Production 0.25 m
pHEMT and Passives Processes
TOM3 FET Models Available
Applications
Highly Efficient and Linear
Power Amplifiers
Low Loss, High Isolation
Switches for Wireless Trans-
ceivers and Basestations
Higher Supply Voltage Applica-
tions
Integrated RF Front Ends
LNA, SW, PA
General Description
TriQuint's 0.5 m pHEMT process is based on our production
released 0.25 m gate process. TQPHT substitutes lower cost
optical lithography in place of e-beam and adds TriQuint's
unique thick metal scheme. This process is targeted for high
efficiency and linearity in power amplifiers, low noise amplifiers,
and linear, low loss and high isolation RF switch applications
.
The TQPHT process offers a D-Mode pHEMT with a 0.8 V
pinch off. The three metal interconnecting layers are encapsu-
lated in a high performance dielectric that allows wiring flexibil-
ity, optimized die size and plastic packaging simplicity. Precision
NiCr resistors and high value MIM capacitors are included al-
lowing higher levels of integration, while maintaining smaller,
cost effective die sizes.
Page 1 of 5; Rev 2.0 7/22/03
Isolation Implant
Pseudomorphic
Channel
N+
Metal 2 - 4um
Metal 1
Metal 2
Dielectric
Metal 1 - 2um
Dielectric
Dielectric
Metal 0
Nitride
Isolation Implant
Metal 1
MIM Metal
NiCr
pHEMT
NiCr Resistor
MIM Capacitor
Semi-Insulating GaAs Substrate
Isolation Implant
Pseudomorphic
Channel
N+
Metal 2 - 4um
Metal 1
Metal 2
Dielectric
Metal 1 - 2um
Dielectric
Dielectric
Metal 0
Nitride
Isolation Implant
Metal 1
MIM Metal
Isolation Implant
Pseudomorphic
Channel
N+
Metal 2 - 4um
Metal 1
Metal 2
Dielectric
Metal 1 - 2um
Dielectric
Dielectric
Metal 0
Nitride
Isolation Implant
Metal 1
MIM Metal
NiCr
pHEMT
NiCr Resistor
MIM Capacitor
Semi-Insulating GaAs Substrate
0.5 um pHEMT Device Cross-Section
Fully Released
Production Process
Production Process
TQPHT
0.5 um pHEMT Foundry Service
Semiconductors for Communications
www.triquint.com
TriQuint Semiconductor
2300 NE Brookwood Pkwy
Hillsboro, Oregon 97124
Phone: 503-615-9000
Fax: 503-615-8905
Email: info@triquint.com
Page 2 of 5; Rev 2.0 7/22/03
Process Details @ Vds = 3.0V
Element
Parameter
Value
Units
D-Mode pHEMT
Vp (1uA/um)
-0.8
V
Idss
200
mA/mm
Idh (Ig=1ua/um)
500
mA/mm
Gm (50% Idss)
350
mS/mm
Breakdown, Vds
15 min
V
Ft @ 50% Idss
25
GHz
Common Process Element Details
Gate Length
0.5
m
Interconnect
3
Metal Layers
MIM Caps
Value
630
pF/mm2
Resistors
NiCr
50
Ohms/sq
Bulk
285
Ohms/sq
Vias
Yes
Mask Layers
No Vias
12
With Vias
14
Fmax @ 50% Idss
90
GHz
Coff @Vds=0,
Vgs= -2.5V
0.3
pF/mm
Ron @ Idss
1.8
Ohm-mm
TQPHT
Process
Details
Maximum
Ratings
Storage Temperature Range
-65 to +150
Deg C
Operating Temperature Range
-55 to +150
Deg C
Transistor (Vs open; Idg =
1uA/um)
17
V
Capacitor
20
V
Production Process
TQPHT
0.5 um pHEMT Foundry Service
TriQuint Semiconductor
2300 NE Brookwood Pkwy
Hillsboro, Oregon 97124
Phone: 503-615-9000
Fax: 503-615-8905
Email: info@triquint.com
Semiconductors for Communications
www.triquint.com
Page 3 of 5; Rev 2.0 7/22/03
f req (100.0MHz to 26.10GHz)
S(
1
,
1
)
S(
2
,
2
)
-8
-6
-4
-2
0
2
4
6
8
-10
10
f req (100.0MHz to 26.10GHz)
S(
1,
2
)
/
0
.
0
5
S(
2,
1)
S-Parameter Data:
300 um Device; Vds = 3.0V; 50% Idss
Ft versus Vgs as a function of Vds:
300
um
Device
Ft versus Vgs
0
5
10
15
20
25
30
35
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
Vgs (Volts)
Ft
Vds=1.5V
Vds=3.0V
I-V Characteristics:
300 um Device
Gmax versus Vgs and Frequency:
300
um
Device
Production Process
TQPHT
0.5 um pHEMT Foundry Service
TriQuint Semiconductor
2300 NE Brookwood Pkwy
Hillsboro, Oregon 97124
Semiconductors for Communications
www.triquint.com
Page 4 of 5; Rev 2.0 7/22/03
Phone: 503-615-9000
Fax: 503-615-8905
Email: info@triquint.com
Ids versus Vgs
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0
1
2
3
4
5
6
7
8
9
Vds (Volts)
Id
s
(
A
)
Vgs=-0.8V
Vgs=-0.6V
Vgs=-0.4V
Vgs=-0.2V
Vgs=0V
Vgs=0.2V
Vgs=0.4V
Vgs=0.6V
Gm ax versus Vgs
12
14
16
18
20
22
24
26
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
Vgs (Volts)
Gm
a
x
(
d
B
)
F req@ 2.1GH z
F req@ 4.1GH z
F req@ 6.1GH z
F req@ 8.1GH z
F req@ 10.1GH z
F req@ 12.1GH z
Design Tool Status
Complete Design Manual Now
Device Library of circuit elements: FETs, diodes, thin
film resistors, capacitors, inductors
Design Kit for Agilent's ADS design environment
Design Kit planned for AWR Microwave Office
Layout Library in GSD II format
Cadence Development Kit with PCells
Layout Rule Sets for Design Rule Check
Qualified package models for supported package styles
Please contact your local TriQuint Semiconductor Representative/ Distributor
or Foundry Services Division for Additional information:
E-mail: sales@triquint.com
Phone: (503) 615-9000
Fax: (503) 615-8905
Production Process
TQPHT
0.5 um pHEMT Foundry Service
TriQuint Semiconductor
2300 NE Brookwood Pkwy
Hillsboro, Oregon 97124
Phone: 503-615-9000
Fax: 503-615-8905
Email: info@triquint.com
Semiconductors for Communications
www.triquint.com
Page 5 of 5; Rev 2.0 7/22/03
Prototyping and Development
Prototype Development Quick Turn (PDQ):
Shared mask set
Run monthly
Hot Lot cycle time
Prototype Wafer Option (PWO):
Customer-specific masks; Customer schedule
2 wafers delivered
Hot Lot cycle time
With thinning and sawing; optional backside
vias
Process Qualification Status
Mature process based on TQTx, 150-mm process
Process released to production
Full 150mm wafer Process Qualification complete
For more information on Quality and Reliability, con-
tact TriQuint or visit:
www.triquint.com/manufacturing/QR/
Applications Support Services
Tiling of GDSII stream files including PCM
Design Rule Check services
Layout Versus Schematic check services
Packaging Development Engineering
Test Development Engineering:
On-wafer
Packaged parts
Thermal Analysis Engineering
Yield Enhancement Engineering
Part Qualification Services
Failure Analysis
Training
GaAs Design Classes:
Half-Day Introduction; Upon request
Four-Day Technical Training; Fall and Spring at
TriQuint Oregon facility
For Training & PDQ Schedules, please visit:
www.triquint.com/foundry/
Manufacturing Services
Mask making
Production 150-mm wafer fab
Wafer Thinning
Wafer Sawing
Substrate Vias
DC Diesort Testing
RF On-wafer testing
Plastic Packaging
RF Packaged Part Testing
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