CMOS IC 2-WIRE BUS
64K ELECTRICALLY ERASABLE PROGRAMMABLE ROM
8K X 8 BIT EEPROM
Turbo IC, Inc.
24C64
SERIAL DATA (SDA)
SDA is a bidirectional pin used to transfer data
in and out of the Turbo IC 24C64. The pin is an
open-
WRITE PROTECT (WP)
When the write protect input is connected to Vcc,
the upper quadrant of memory (1800-1FFFH) is
protected against write operations. For normal
write operation, the write protect pin should be
grounded. When this pin is left unconnected, WP
is interpreted as zero.
PIN DESCRIPTION
DEVICE ADDRESSES (A2-A0)
The address inputs are used to define the 3 least
significant bits of the 7-bit device address code -
1010 (A2) (A1) (A0). These pins can be con-
nected either high or low. A maximum of eight
Turbo IC 24C64 can be connected in parallel,
each with a unique device address. When these
pins are left unconnected, the device addresses
are interpreted as zero.
drain output. A pullup resistor must be connected
from SDA to Vcc.
SERIAL CLOCK (SCL)
The SCL input synchronizes the data on the SDA
bus. It is used in conjunction with SDA to define
the start and stop conditions. It is also used in
conjunction with SDA to transfer data to and from
the Turbo IC 24C64.
1
2
3
4
5
6
7
8
A0
A1
A2
GND
VCC
WP
SCL
SDA
8 pin PDIP
1
2
3
4
5
6
7
8
A0
A1
A2
GND
VCC
WP
SCL
SDA
8 pin SOIC
PIN DESCRIPTION
DESCRIPTION:
The Turbo IC 24C64 is a serial 64K EEPROM fabricated
with Turbo's proprietary, high reliability, high performance
CMOS technology. It's 64K of memory is organized as 8,192
x 8 bits. The memory is configured as 256 pages with each
page containing 32 bytes. This device offers significant ad-
vantages in low power and low voltage applications.
The Turbo IC 24C64 uses the extended IC addressing pro-
tocol and 2-wire serial interface which includes a bidirec-
tional serial data bus synchronized by a clock. It offers a
flexible byte write and a faster 32-byte page write. The data
in the upper quadrant of memory can be protected by a
write protect pin.
The Turbo IC 24C64 is assembled in either a 8-pin PDIP or
8-pin SOIC package. Pin #1 (A0), #2 (A1), and #3 (A2) are
device address input pins which are hardwired by the user.
Pin #4 is the ground (Vss). Pin #5 is the serial data (SDA)
pin used for bidirectional transfer of data. Pin #6 is the serial
clock (SCL) input pin. Pin #7 is the write protect (WP) input
pin, and Pin #8 is the power supply (Vcc) pin.
All data is serially transmitted in bytes (8 bits) on the SDA
bus. To access the Turbo IC 24C64 (slave) for a read or
write operation, the controller (master) issues a start condi-
tion by pulling SDA from high to low while SCL is high. The
master then issues the device address byte which consists
of 1010 (A2) (A1) (A0) (R/W). The 4 most significant bits
(1010) are a device type code signifying an EEPROM de-
vice. The A[2:0] bits represent the input levels on the 3 de-
vice address input pins. The read/write bit determines
whether to do a read or write operation. After each byte is
transmitted, the receiver has to provide an acknowledge by
pulling the SDA bus low on the ninth clock cycle. The ac-
knowledge is a handshake signal to the transmitter indicat-
ing a successful data transmission.
FEATURES :
Extended Power Supply Voltage
Single Vcc for Read and Programming
(Vcc = 2.7 V to 5.5 V)
Low Power (Isb = 2a @ 5.5 V)
Extended IC Bus, 2-Wire Serial Interface
Support Byte Write and Page Write (32 Bytes)
Automatic Page write Operation (maximum 10 ms)
Internal Control Timer
Internal Data Latches for 32 Bytes
Hardware Data Protection by Write Protect Pin
High Reliability CMOS Technology with EEPROM Cell
Endurance : 1,000,000 Cycles
Data Retention : 100 Y
ears
1
24C64
DESCRIPTION (Continued)
For a write operation, the master issues a start condition,
device address byte, 2 memory address bytes, and then up
to 32 data bytes. The Turbo IC 24C64 acknowledges after
each byte transmission. To terminate the transmission, the
master issues a stop condition by pulling SDA from low to
high while SCL is high.
For a read operation, the master issues a start condition and
a device address byte. The Turbo IC 24C64 acknowledges,
and then transmits a data byte, which is accessed from the
EEPROM memory. The master acknowledges, indicating that
it requires more data bytes. The Turbo IC 24C64 transmits
more data bytes, with the memory address counter auto-
matically incrementing for each data byte, until the master
does not acknowledge, indicating that it is terminating the
transmission. The master then issues a stop condition.
DEVICE OPERATION:
BIDIRECTIONAL BUS PROTOCOL:
The Turbo IC 24C64 follows the extended IC bus protocol.
The protocol defines any device that sends data onto the
SDA bus as a transmitter, and the receiving device as a re-
ceiver. The device controlling the transfer is the master and
the device being controlled is the slave. The master always
initiates the data transfers, and provides the clock for both
transmit and receive operations. The Turbo IC 24C64 acts as
a slave device in all applications. Either the master or the
slave can take control of the SDA bus, depending on the
requirement of the protocol.
START/STOP CONDITION AND DATA TRANSITIONS:
While SCL clock is high, a high to low transition on the SDA
bus is recognized as a START condition which precedes any
read or write operation. While SCL clock is high, a low to
high transition on the SDA bus is recognized as a STOP con-
dition which terminates the communication and places the
Turbo IC 24C64 into standby mode. All other data transitions
on the SDA bus must occur while SCL clock is low to ensure
proper operation.
ACKNOWLEDGE:
All data is serially transmitted in bytes (8 bits) on the SDA
bus. The acknowledge protocol is used as a handshake sig-
nal to indicate successful transmission of a byte of data. The
bus transmitter, either the master or the slave (Turbo IC
24C64), releases the bus after sending a byte of data on the
SDA bus. The receiver pulls the SDA bus low during the ninth
clock cycle to acknowledge the successful transmission of a
byte of data. If the SDA is not pulled low during the ninth
clock cycle, the Turbo IC 24C64 terminates the data trans-
mission and goes into standby mode.
For the write operation, the Turbo IC 24C64 acknowledges
after the device address byte, acknowledges after each
memory address byte, and acknowledges after each subse-
quent data byte.
For the read operation, the Turbo IC 24C64 acknowledges
after the device address byte. Then the Turbo IC 24C64 trans-
mits each subsequent data byte, and the master acknowl-
edges after each data byte transfer, indicating that it requires
more data bytes. The Turbo IC 24C64 monitors the SDA bus
for the acknowledge. To terminate the transmission, the mas-
ter does not acknowledge, and then sends a stop condition.
Write Cycle Timing
Note: The write cycle time t
WC
is the time from a valid stop condition of a write sequence to the end of the internal clear / write cycle.
SCL
SDA
WORD n
8th BIT
ACK
STOP
CONDITION
START
CONDITION
t
WC
Turbo IC, Inc.
2
24C64
Data Valid
Turbo IC, Inc.
Output Acknowledge
Start and Stop Definition
SDA
SCL
DATA STABLE
DATA STABLE
DATA
CHANGE
SDA
SCL
START
STOP
SCL
DATA IN
DATA OUT
1
8
9
ACKNOWLEDGE
START
3
24C64
DEVICE ADDRESSING:
Following the start condition, the master will issue a device
address byte consisting of 1010 (A2) (A1) (A0) (R/W) to ac-
cess the selected Turbo IC 24C64 for a read or write opera-
tion. The A[2:0] bits must match with the address input pins
of the selected Turbo IC 24C64. If there is a match, the se-
lected Turbo IC 24C64 acknowledges during the ninth clock
cycle by pulling the SDA bus low. If there is no match, the
Turbo IC 24C64 does not acknowledge during the ninth clock
cycle and goes into standby mode. The (R/W) bit is a high (1)
for read and low (0) for write.
DATA INPUT DURING WRITE OPERATION:
During the write operation, the Turbo IC 24C64 latches the
SDA bus signal on the rising edge of the SCL clock.
DATA OUTPUT DURING READ OPERATION:
During the read operation, the Turbo IC 24C64 serially shifts
the data onto the SDA bus on the falling edge of the SCL
clock.
MEMORY ADDRESSING:
The memory address is sent by the master in the form of 2
memory address bytes. The memory address bytes can only
be sent as part of a write operation. The most significant
address byte XXX (B12) (B11) (B10) (B9) (B8) is sent first,
where X represents "don't care". Then the least significant
address byte (B7) (B6) (B5) (B4) (B3) (B2) (B1) (B0) is sent
last.
BYTE WRITE OPERATION:
The master initiates the byte write operation by issuing a
start condition, followed by the device address byte 1010
(A2) (A1) (A0) 0, followed by 2 memory address bytes, fol-
lowed by one data byte, followed by an acknowledge, then a
stop condition. After each byte transfer, the Turbo IC 24C64
acknowledges the successful data transmission by pulling
the SDA bus low. The stop condition starts the internal
EEPROM write cycle, and all inputs are disabled until the
completion of the write cycle. If the WP pin is high (1) and the
memory address is within the upper quadrant (1800-1FFFH)
of memory, then the stop condition does not start the inter-
nal write cycle and the Turbo IC 24C64 is immediately ready
for the next command.
PAGE WRITE OPERATION:
The master initiates the page write operation by issuing a
start condition, followed by the device address byte 1010
(A2) (A1) (A0) 0, followed by 2 memory address bytes, fol-
lowed by up to 32 data bytes, followed by an acknowledge,
then a stop condition. After each byte transfer, the Turbo
IC24C64 acknowledges the successful data transmission by
pulling SDA low. After each data byte transfer, the memory
address counter is automatically incremented by one. The
stop condition starts the internal EEPROM write cycle only if
the stop condition occurs in the clock cycle immediately fol-
lowing the acknowledge (10th clock cycle). All inputs are dis-
abled until the completion of the write cycle. If the WP pin is
high (1) and the memory address is within the upper quad-
rant (1800-1FFFH) of memory, then the stop condition does
not start the internal write cycle, and the Turbo IC 24C64 is
immediately ready for the next command.
POLLING ACKNOWLEDGE:
During the internal write cycle of a write operation in the Turbo
IC 24C64, the completion of the write cycle can be detected
by polling acknowledge. The master starts acknowledge poll-
ing by issuing a start condition, then followed by the device
address byte 1010 (A2) (A1) (A0) 0. If the internal write cycle
is finished, the Turbo IC 24C64 acknowledges by pulling the
SDA bus low. If the internal write cycle is still ongoing, the
Turbo IC 24C64 does not acknowledge because it's inputs
are disabled. Therefore, the device will not respond to any
command. By using polling acknowledge, the system delay
for write operations can be reduced. Otherwise, the system
needs to wait for the maximum internal write cycle time, tWC,
given in the spec.
POWER ON RESET:
The Turbo IC 24C64 has a Power On Reset circuit (POR) to
prevent data corruption and accidental write operations dur-
ing power up. On power up, the internal reset signal is on
and the Turbo IC 24C64 will not respond to any command
until the VCC voltage has reached the POR threshold value.
Turbo IC, Inc.
4
24C64
Turbo IC, Inc.
Device Address
1
0
1
0
A
2
A
1
A
0
R/W
MSB
LSB
* = Don't care bits
SDA LINE
DEVICE
ADDRESS
FIRST
WORD ADDRESS (n)
SECOND
WORD ADDRESS (n)
DATA (n)
S
T
O
P
A
C
K
A
C
K
L
S
B
A
C
K
M
S
B
L
S
B
R
/
W
A
C
K
S
T
A
R
T
W
R
I
T
E
* * *
M
S
B
A
C
K
//
//
DATA (n + x)
Page Write
Byte Write
SDA LINE
DEVICE
ADDRESS
FIRST
WORD ADDRESS
SECOND
WORD ADDRESS
DATA
S
T
O
P
A
C
K
A
C
K
L
S
B
A
C
K
M
S
B
L
S
B
R
/
W
A
C
K
S
T
A
R
T
W
R
I
T
E
M
S
B
* * *
5
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