CMOS IC 2-WIRE BUS
128K/256K ELECTRICALLY ERASABLE PROGRAMMABLE ROM
16K/32K X 8 BIT EEPROM
Turbo IC, Inc.
24C128/24C256
SERIAL DATA (SDA)
SDA is a bidirectional pin used to transfer data
in and out of the Turbo IC 24C128/24C256. The
pin is an open-drain output. A pull-up resistor
WRITE PROTECT (WP)
When the write protect input is connected to Vcc,
the entire memory is protected against write op-
erations. For normal write operation, the write
protect pin should be grounded. When this pin is
left unconnected, WP is interpreted as zero.
PIN DESCRIPTION
DEVICE ADDRESSES (A2-A0)
The address inputs are used to define the 3 least
significant bits of the 7-bit device address code -
1010 (A2) (A1) (A0). These pins can be con-
nected either high or low. A maximum of eight
Turbo IC 24C128/24C256 can be connected in
parallel, each with a unique device address. When
these pins are left unconnected, the device ad-
dresses are interpreted as zero.
must be connected from SDA to Vcc.
SERIAL CLOCK (SCL)
The SCL input synchronizes the data on the SDA
bus. It is used in conjunction with SDA to define
the start and stop conditions. It is also used in
conjunction with SDA to transfer data to and from
the Turbo IC 24C128/24C256.
1
2
3
4
5
6
7
8
A0
A1
A2
GND
VCC
WP
SCL
SDA
8 pin PDIP
1
2
3
4
5
6
7
8
A0
A1
A2
GND
VCC
WP
SCL
SDA
8 pin SOIC
PIN DESCRIPTION
DESCRIPTION:
The Turbo IC 24C128/24C256 is a serial 128K/256K
EEPROM fabricated with Turbo's proprietary, high reliabil-
ity, high performance CMOS technology. It's 128K/256K of
memory is organized as 16384/32768 x 8 bits. The memory
is configured as 256/512 pages with each page containing
64 bytes. This device offers significant advantages in low
power and low voltage applications.
The Turbo IC 24C128/24C256 uses the extended IC ad-
dressing protocol and 2-wire serial interface which includes
a bidirectional serial data bus synchronized by a clock. It
offers a flexible byte write and a faster 64-byte page write.
The entire memory can be protected by the write protect
pin.
The Turbo IC 24C128/24C256 is assembled in either a 8-
pin PDIP or 8-pin SOIC package. Pin #1 (A0), #2 (A1), and
#3 (A2) are device address input pins which are hardwired
by the user. Pin #4 is the ground (Vss). Pin #5 is the serial
data (SDA) pin used for bidirectional transfer of data. Pin #6
is the serial clock (SCL) input pin. Pin #7 is the write protect
(WP) input pin, and Pin #8 is the power supply (Vcc) pin.
All data is serially transmitted in bytes (8 bits) on the SDA
bus. To access the Turbo IC 24C128/24C256 (slave) for a
read or write operation, the controller (master) issues a start
condition by pulling SDA from high to low while SCL is high.
The master then issues the device address byte which con-
sists of 1010 (A2) (A1) (A0) (R/W). The 4 most significant
bits (1010) are a device type code signifying an EEPROM
device. The A[2:0] bits represent the input levels on the 3
device address input pins. The read/write bit determines
whether to do a read or write operation. After each byte is
transmitted, the receiver has to provide an acknowledge by
pulling the SDA bus low on the ninth clock cycle. The ac-
knowledge is a handshake signal to the transmitter indicat-
ing a successful data transmission.
FEATURES :
Extended Power Supply Voltage
Single Vcc for Read and Programming
(Vcc = 2.7 V to 5.5 V)
Low Power (Isb = 2a @ 5.5 V)
Extended IC Bus, 2-Wire Serial Interface
Support Byte Write and Page Write (64 Bytes)
Automatic Page write Operation (maximum 10 ms)
Internal Control Timer
Internal Data Latches for 64 Bytes
Hardware Data Protection by Write Protect Pin
High Reliability CMOS Technology
EEPROM Cell
Endurance : 1,000,000 Cycles
Data Retention : 100 Y
ears
8 pin JDEC 300 mil wide PDIP AND 8 pin 150 mil wide
SOIC packages
1
PRODUCT PRELIMINARY
DESCRIPTION (Continued)
For a write operation, the master issues a start condition,
device address byte, 2 memory address bytes, and then up
to 64 data bytes. The Turbo IC 24C128/24C256 acknowledges
after each byte transmission. To terminate the transmission,
the master issues a stop condition by pulling SDA from low
to high while SCL is high.
For a read operation, the master issues a start condition and
a device address byte. The Turbo IC 24C128/24C256 ac-
knowledges, and then transmits a data byte, which is ac-
cessed from the EEPROM memory. The master acknowl-
edges, indicating that it requires more data bytes. The Turbo
IC 24C128/24C256 transmits more data bytes, with the
memory address counter automatically incrementing for each
data byte, until the master does not acknowledge, indicating
that it is terminating the transmission. The master then is-
sues a stop condition.
DEVICE OPERATION:
BIDIRECTIONAL BUS PROTOCOL:
The Turbo IC 24C128/24C256 follows the extended IC bus
protocol. The protocol defines any device that sends data
onto the SDA bus as a transmitter, and the receiving device
as a receiver. The device controlling the transfer is the mas-
ter and the device being controlled is the slave. The master
always initiates the data transfers, and provides the clock for
both transmit and receive operations. The Turbo IC 24C128/
24C256 acts as a slave device in all applications. Either the
master or the slave can take control of the SDA bus, de-
pending on the requirement of the protocol.
START/STOP CONDITION AND DATA TRANSITIONS:
While SCL clock is high, a high to low transition on the SDA
bus is recognized as a START condition which precedes any
read or write operation. While SCL clock is high, a low to
high transition on the SDA bus is recognized as a STOP con-
dition which terminates the communication and places the
Turbo IC 24C128/24C256 into standby mode. All other data
transitions on the SDA bus must occur while SCL clock is
low to ensure proper operation.
ACKNOWLEDGE:
All data is serially transmitted in bytes (8 bits) on the SDA
bus. The acknowledge protocol is used as a handshake sig-
nal to indicate successful transmission of a byte of data. The
bus transmitter, either the master or the slave (Turbo IC
24C128/24C256), releases the bus after sending a byte of
data on the SDA bus. The receiver pulls the SDA bus low
during the ninth clock cycle to acknowledge the successful
transmission of a byte of data. If the SDA is not pulled low
during the ninth clock cycle, the Turbo IC 24C128/24C256
terminates the data transmission and goes into standby mode.
For the write operation, the Turbo IC 24C128/24C256 ac-
knowledges after the device address byte, acknowledges
after each memory address byte, and acknowledges after
each subsequent data byte.
For the read operation, the Turbo IC 24C128/24C256 ac-
knowledges after the device address byte. Then the Turbo IC
24C128/24C256 transmits each subsequent data byte, and
the master acknowledges after each data byte transfer, indi-
cating that it requires more data bytes. The Turbo IC 24C128/
24C256 monitors the SDA bus for the acknowledge. To ter-
minate the transmission, the master does not acknowledge,
and then sends a stop condition.
Write Cycle Timing
Note: The write cycle time t
WC
is the time from a valid stop condition of a write sequence to the end of the internal clear / write cycle.
SCL
SDA
WORD n
8th BIT
ACK
STOP
CONDITION
START
CONDITION
t
WC
Turbo IC, Inc.
2
24C128/24C256
PRODUCT PRELIMINARY
Data Valid
Turbo IC, Inc.
Output Acknowledge
Start and Stop Definition
SDA
SCL
DATA STABLE
DATA STABLE
DATA
CHANGE
SDA
SCL
START
STOP
SCL
DATA IN
DATA OUT
1
8
9
ACKNOWLEDGE
START
3
24C128/24C256
PRODUCT PRELIMINARY
DEVICE ADDRESSING:
Following the start condition, the master will issue a device
address byte consisting of 1010 (A2) (A1) (A0) (R/W) to ac-
cess the selected Turbo IC 24C128/24C256 for a read or
write operation. The A[2:0] bits must match with the address
input pins of the selected Turbo IC 24C128/24C256. If there
is a match, the selected Turbo IC 24C128/24C256 acknowl-
edges during the ninth clock cycle by pulling the SDA bus
low. If there is no match, the Turbo IC 24C128/24C256 does
not acknowledge during the ninth clock cycle and goes into
standby mode. The (R/W) bit is a high (1) for read and low (0)
for write.
DATA INPUT DURING WRITE OPERATION:
During the write operation, the Turbo IC 24C128/24C256
latches the SDA bus signal on the rising edge of the SCL
clock.
DATA OUTPUT DURING READ OPERATION:
During the read operation, the Turbo IC 24C128/24C256 se-
rially shifts the data onto the SDA bus on the falling edge of
the SCL clock.
MEMORY ADDRESSING:
The memory address is sent by the master in the form of 2
memory address bytes. The memory address bytes can only
be sent as part of a write operation. The most significant
address byte B(14) B(13) (B12) (B11) (B10) (B9) (B8) is sent
first, where B(14) is a "don't care" bit in the 24C128. Then the
least significant address byte (B7) (B6) (B5) (B4) (B3) (B2)
(B1) (B0) is sent last.
BYTE WRITE OPERATION:
The master initiates the byte write operation by issuing a
start condition, followed by the device address byte 1010
(A2) (A1) (A0) 0, followed by 2 memory address bytes, fol-
lowed by one data byte, then a stop condition. After each
byte transfer, the Turbo IC 24C128/24C256 acknowledges
the successful data transmission by pulling the SDA bus low.
The stop condition starts the internal EEPROM write cycle,
and all inputs are disabled until the completion of the write
cycle. If the WP pin is high, then the stop condition does not
start the internal write cycle and the Turbo IC 24C128/24C256
is immediately ready for the next command.
PAGE WRITE OPERATION:
The master initiates the page write operation by issuing a
start condition, followed by the device address byte 1010
(A2) (A1) (A0) 0, followed by 2 memory address bytes, fol-
lowed by up to 64 data bytes, then a stop condition. After
each byte transfer, the Turbo IC 24C128/24C256 acknowl-
edges the successful data transmission by pulling SDA low.
After each data byte transfer, the
memory address counter is automatically incremented by
one. The stop condition starts the internal EEPROM write
cycle only if the stop condition occurs in the clock cycle im-
mediately following the acknowledge (10th clock cycle). All
inputs are disabled until the completion of the write cycle. If
the WP pin is high (1), then the stop condition does not start
the internal write cycle, and the Turbo IC 24C128/24C256 is
immediately ready for the next command.
POLLING ACKNOWLEDGE:
During the internal write cycle of a write operation in the Turbo
IC 24C128/24C256, the completion of the write cycle can be
detected by polling acknowledge. The master starts acknowl-
edge polling by issuing a start condition, then followed by the
device address byte 1010 (A2) (A1) (A0) 0. If the internal
write cycle is finished, the Turbo IC 24C128/24C256 acknowl-
edges by pulling the SDA bus low. If the internal write cycle is
still ongoing, the Turbo IC 24C128/24C256 does not acknowl-
edge because it's inputs are disabled. Therefore, the device
will not respond to any command. By using polling acknowl-
edge, the system delay for write operations can be reduced.
Otherwise, the system needs to wait for the maximum inter-
nal write cycle time, tWC, given in the spec.
POWER ON RESET:
The Turbo IC 24C128/24C256 has a Power On Reset circuit
(POR) to prevent data corruption and accidental write op-
erations during power up. On power up, the internal reset
signal is on and the Turbo IC 24C128/24C256 will not re-
spond to any command until the VCC voltage has reached
the POR threshold value.
Turbo IC, Inc.
4
24C128/24C256
PRODUCT PRELIMINARY
Turbo IC, Inc.
Device Address
1
0
1
0
A
2
A
1
A
0
R/W
MSB
LSB
* = Don't care bits
! = Don't care bit for 24C128
Page Write
Byte Write
5
24C128/24C256
PRODUCT PRELIMINARY
SDA LINE
DEVICE
ADDRESS
FIRST
WORD ADDRESS
SECOND
WORD ADDRESS
DATA
S
T
O
P
A
C
K
A
C
K
L
S
B
A
C
K
M
S
B
L
S
B
R
/
W
A
C
K
S
T
A
R
T
W
R
I
T
E
M
S
B
128K
* !
M
S
B
256K
SDA LINE
DEVICE
ADDRESS
FIRST
WORD ADDRESS (n)
SECOND
WORD ADDRESS (n)
DATA (n)
S
T
O
P
A
C
K
A
C
K
L
S
B
A
C
K
M
S
B
L
S
B
R
/
W
A
C
K
S
T
A
R
T
W
R
I
T
E
* !
M
S
B
256K
A
C
K
//
//
DATA (n + x)
M
S
B
128K
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