PRELIMINARY
March 17, 2003
www.ubicom.com
2001-2003 Ubicom, Inc. All rights reserved.
1
1.0
Product Highlights
The Ubicom IP2012TM and IP2022TM Wireless Network
Processors combine support for communication physical
layer, Internet protocol stack, device-specific application,
and device-specific peripheral software modules in a
single chip, and are reconfigurable over the Internet. They
can be programmed, and reprogrammed, using pre-built
software modules and configuration tools to create true
single-chip solutions for a wide range of device-to-device
and device-to-human communication applications. High
speed communication interfaces are available via on-chip
hardware Serializer/Deserializer (SerDes) blocks. These
full-duplex blocks allow the IP2022 or IP2012 to be used
in a variety of communication bridging applications. Each
SerDes block is capable of supporting 10Base-T Ethernet
(MAC and PHY), USB, GPSI, SPI, or UART. The high-
speed operating frequency, combined with most
instructions executing in a single cycle, delivers the
throughput needed for emerging network connectivity
applications. A flash-based program memory allows both
in-system and runtime reprogramming. The IP2022 and
IP2012 implement most peripheral, communications and
control functions via software modules (ipModuleTM
software), replacing traditional hardware for maximum
system design flexibility. This approach allows rapid,
inexpensive product design and, when needed, quick and
easy reconfiguration to accommodate changes in market
needs or industry standards.
Key Features:
Designed to support single-chip networked solutions
Fast processor core
64kB Flash program memory
16kB SRAM data/program memory
4kB SRAM data memory
Two SerDes communication blocks supporting com-
mon PHYs (Ethernet, USB, UARTs, etc.) and bridging
applications (IP2012 has only one SerDes unit)
Advanced RISC processors
IP2022 -- 120 and 160 MHz versions
IP2012 -- 120 MHz version
High speed packet processing
Instruction set optimized for communication functions
Supports software implementation of traditional hard-
ware functions
In-system reprogrammable for highest flexibility
Run time self-programmable
Vpp = Vcc supply voltage
Figure 1-1 IP2012 / IP2022 Block Diagram
515-063b.eps
IP2022/IP2012
10Base-T Ethernet
(MAC/PHY on chip)
USB 1.1 (SIE on chip)
GPSI
SPI
UART/Modem
Bluetooth HCI
Customer Application
HTTP/SMTP/TFTP
TCP/UDP
IP/ICMP
Network Access Layer
ipModule Software
PHY Firmware
ipOS Operating System
ISP/ISD
Interface
8-Input
10-Bit
A/DC
PLL
Clock
Multiplier
5
Timers
External
Memory
Interface
4-Kbyte
Data
RAM
16-Kbyte
Inst./Data
RAM
64-Kbyte
Flash
Memory
Internet
Processor
CPU
8/16-Bit
Parallel
Slave Port
ISA (802.11b)
Mini-PCI/Cardbus
(802.11g/802.11a)
I2C
General-Purpose I/O
Choices for
Communication:
10Base-T Ethernet
(MAC/PHY on chip)
USB 1.1 (SIE on chip)
GPSI
SPI
UART/Modem
Bluetooth HCI
Host Bus
Choices for
Communication:
TM
High-Speed
Serial Unit 1
(SERDES)
High-Speed
Serial Unit 2
(SERDES)
Not available on IP2012
General
Purpose
I/O Ports
IP2012 / IP2022 Wireless Network Processors
Features and Performance Optimized for Network Connectivity
2
www.ubicom.com
IP2012 / IP2022 Data Sheet
1.0 Product Highlights
1
1.1
Additional Features. . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2
Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2.1
CPU
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2.2
Serializer/Deserializers
. . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2.3
Low-Power Support
. . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2.4
Memory
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2.5
Instruction Set
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2.6
Other Supported Functions
. . . . . . . . . . . . . . . . . . . . . . .5
1.2.7
Programming and Debugging Support
. . . . . . . . . . . . . . .5
2.0 Pin Definitions
6
2.1
PQFP (Plastic Quad Flat Package) for IP2022. . . . . .6
2.2
PQFP (Plastic Quad Flat Package) for IP2012. . . . . .7
2.3
BGA (Micro Ball Grid Array) IP2022-120 Only . . . . .8
2.4
Signal Descriptions -- IP2022 . . . . . . . . . . . . . . . . . .9
2.5
Signal Descriptions -- IP2012 . . . . . . . . . . . . . . . . .12
3.0 System Architecture
15
3.1
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.2
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.3
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.3.1
Loading the Program RAM
. . . . . . . . . . . . . . . . . . . . . .19
3.3.2
Program Counter
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.4
Low Power Support . . . . . . . . . . . . . . . . . . . . . . . . .20
3.4.1
Clock Stop Mode (SLEEP)
. . . . . . . . . . . . . . . . . . . . . .21
3.4.2
Wakeup
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.5
Speed Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.6
Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.7
Interrupt Support. . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.7.1
Interrupt Processing
. . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.7.2
Global Interrupt Enable Bit
. . . . . . . . . . . . . . . . . . . . . .25
3.7.3
Interrupt Latency
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3.7.4
Return From Interrupt
. . . . . . . . . . . . . . . . . . . . . . . . . .25
3.7.5
Disabled Interrupt Resources
. . . . . . . . . . . . . . . . . . . .26
3.8
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3.8.1
Brown-Out Detector
. . . . . . . . . . . . . . . . . . . . . . . . . . .28
3.8.2
Reset and Interrupt Vectors
. . . . . . . . . . . . . . . . . . . . . .28
3.8.3
Register States Following Reset
. . . . . . . . . . . . . . . . . .28
3.9
Clock Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.9.1
External Connections
. . . . . . . . . . . . . . . . . . . . . . . . . .30
3.10
Configuration Block. . . . . . . . . . . . . . . . . . . . . . . . . .31
3.10.1
FUSE0 Register (not run-time programmable)
. . . . . . . . .32
3.10.2
FUSE1 Register (not run-time programmable)
. . . . . . . . .33
3.10.3
TRIM0 Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
4.0 Instruction Set Architecture
35
4.1
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . .35
4.1.1
Pointer Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
4.1.2
Direct Addressing Mode
. . . . . . . . . . . . . . . . . . . . . . . .36
4.1.3
Indirect Addressing Mode
. . . . . . . . . . . . . . . . . . . . . . .36
4.1.4
Indirect-with-Offset Addressing Mode
. . . . . . . . . . . . . . .37
4.2
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
4.2.1
Instruction Formats
. . . . . . . . . . . . . . . . . . . . . . . . . . .38
4.2.2
Instruction Types
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
4.3
Instruction Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.4
Subroutine Call/Return Stack . . . . . . . . . . . . . . . . . .41
4.5
Key to Abbreviations and Symbols . . . . . . . . . . . . . .42
4.6
Instruction Set Summary Tables. . . . . . . . . . . . . . . .42
4.7
Program Memory Instructions. . . . . . . . . . . . . . . . . .47
4.7.1
Flash Timing Control
. . . . . . . . . . . . . . . . . . . . . . . . . .48
4.7.2
Interrupts During Flash Operations
. . . . . . . . . . . . . . . . .48
5.0 Peripherals
49
5.1
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
5.1.1
Port B Interrupts
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
5.1.2
Reading and Writing the Ports
. . . . . . . . . . . . . . . . . . . .50
5.1.3
RxIN Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
5.1.4
RxOUT Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
5.1.5
RxDIR Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
5.1.6
INTED Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
5.1.7
INTF Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
5.1.8
INTE Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
5.1.9
Port Configuration Upon Power-Up
. . . . . . . . . . . . . . . .51
5.2
Timer 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
5.3
Real-Time Timer (RTTMR) . . . . . . . . . . . . . . . . . . . .52
5.4
Multi-Function Timers (T1 and T2) . . . . . . . . . . . . . .54
5.4.1
Timers T1, T2 Operating Modes
. . . . . . . . . . . . . . . . . .54
5.4.2
T1 and T2 Timer Pin Assignments
. . . . . . . . . . . . . . . . .56
5.4.3
T1 and T2 Timer Registers
. . . . . . . . . . . . . . . . . . . . . .56
5.5
Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . .57
5.6
Serializer/Deserializer (SERDES). . . . . . . . . . . . . . .58
5.6.1
SERDES TX/RX Buffers
. . . . . . . . . . . . . . . . . . . . . . . .58
5.6.2
SERDES Configuration
. . . . . . . . . . . . . . . . . . . . . . . . .58
5.6.3
SERDES Interrupts
. . . . . . . . . . . . . . . . . . . . . . . . . . .59
5.6.4
Protocol Modes
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
5.6.5
10base-T Ethernet
. . . . . . . . . . . . . . . . . . . . . . . . . . . .61
5.6.6
USB
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
5.6.7
UART
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
5.6.8
SPI
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
5.6.9
GPSI
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
5.7
Analog to Digital Converter (ADC) . . . . . . . . . . . . . .72
5.7.1
ADC Reference Voltage
. . . . . . . . . . . . . . . . . . . . . . . .72
5.7.2
A/D Converter Registers
. . . . . . . . . . . . . . . . . . . . . . . .72
5.7.3
Using the A/D Converter
. . . . . . . . . . . . . . . . . . . . . . . .73
5.7.4
ADC Result Justification
. . . . . . . . . . . . . . . . . . . . . . . .73
5.8
Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
5.8.1
CMPCFG Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . .73
5.9
Linear Feedback Shift Register (LFSR) . . . . . . . . . .74
5.10
Parallel Slave Peripheral (PSP) . . . . . . . . . . . . . . . .79
5.10.1
PSPCFG Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . .79
5.11
External Memory Interface (IP2022 only) . . . . . . . . .80
5.11.1
EMCFG Register (IP2022 only)
. . . . . . . . . . . . . . . . . . .80
6.0 In-System Programming
83
7.0 Memory Reference
84
7.0.1
Registers (sorted by address)
. . . . . . . . . . . . . . . . . . . .84
7.0.2
Program Memory
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
7.1
Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . .89
7.1.1
ADCCFG Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . .89
7.1.2
ADCTMR Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . .89
7.1.3
CMPCFG Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . .89
7.1.4
EMCFG Register (IP2022 only)
. . . . . . . . . . . . . . . . . . .90
7.1.5
FCFG Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
7.1.6
INTSPD Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
7.1.7
LFSRA Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
7.1.8
PSPCFG Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . .93
7.1.9
RTCFG Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
7.1.10
SxINTE/SxINTF Register
. . . . . . . . . . . . . . . . . . . . . . .95
7.1.11
SxMODE Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . .96
7.1.12
SxRCFG Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . .96
7.1.13
SxRCNT Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . .97
7.1.14
SxRSYNC Register
. . . . . . . . . . . . . . . . . . . . . . . . . . .97
7.1.15
SxSMASK Register
. . . . . . . . . . . . . . . . . . . . . . . . . . .98
7.1.16
SxTCFG Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . .98
7.1.17
SxTMRH/SxTMRL Register
. . . . . . . . . . . . . . . . . . . . . .99
7.1.18
SPDREG Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.1.19
STATUS Register
. . . . . . . . . . . . . . . . . . . . . . . . . . .100
7.1.20
T0CFG Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . .101
7.1.21
TxCFG1H Register
. . . . . . . . . . . . . . . . . . . . . . . . . . .101
7.1.22
TxCFG2H Register
. . . . . . . . . . . . . . . . . . . . . . . . . . .102
7.1.23
TxCFG1L Register
. . . . . . . . . . . . . . . . . . . . . . . . . . .102
7.1.24
TxCFG2L Register
. . . . . . . . . . . . . . . . . . . . . . . . . . .103
7.1.25
TCTRL Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
7.1.26
XCFG Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
8.0 Electrical Characteristics
105
8.1
Absolute Maximum Ratings). . . . . . . . . . . . . . . . . .105
8.2
DC Specifications: IP2022-120, IP2012-120 . . . . .106
8.3
DC Specifications: IP2022-160. . . . . . . . . . . . . . . .108
8.4
AC Specifications: IP2022-120, IP2012-120 . . . . .110
8.5
AC Specifications: IP2022-160 . . . . . . . . . . . . . . . .111
8.6
Comparator DC and AC Specifications . . . . . . . . .112
8.7
ADC 10-bit Converter DC and AC Specifications . .112
9.0 Package Dimensions
113
9.1
PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
9.2
BGA (available for IP2022-120 only) . . . . . . . . . .114
10.0 Part Numbering
115
IP2012 / IP2022 Data Sheet
www.ubicom.com
3
1.1
Additional Features
Internet Processor Capabilities
Foundation for Highly Flexible Connectivity Solution
Performance: 120 MIPS @ 120 MHz,
160 MIPS @ 160 MHz
Predictable execution for hard real-time applications
Fast and deterministic 3-cycle (25ns @120MHz,
18.75ns @ 160 MHz) internal interrupt response
Hardware save/store of key registers
Functions implemented via software tightly coupled
with hardware assist peripherals
Multiple Networking Protocols and Physical Layer
Support Hardware
Two full-duplex serializer/deserializer (SERDES)
channels (IP2022 has two, IP2012 has one)
Flexible to support 10Base-T, GPSI, SPI, UART,
USB protocols
Two channels for protocol bridging
On-chip squelch function for 10Base-T Ethernet
on each SERDES
Four hardware LFSR (Linear Feedback Shift Regis-
ter) units
CRC generation/checking
Data whitening
Encryption
Memory
64-Kbyte (32K
16) on-chip program flash memory
16-Kbyte (8K
16) on-chip program/data RAM
4-Kbyte on-chip linear-addressed data RAM
Self-programming with built-in charge pump: instruc-
tions to read, write, and erase flash memory
Addresses up to 2 Mbytes of external memory
(IP2022 only)
CPU Features
RISC engine core
IP2022-120, IP2012-120
DC to 120 MHz operation
8.33 ns instruction cycle at max frequency
IP2022-160
DC to 120 MHz and 160 MHz operation only
6.25 ns instruction cycle at max frequency
Compact 16-bit fixed-length instructions
Single-cycle instruction execution on most instruc-
tions (3 cycles for jumps and calls)
Sixteen-level hardware stack for high-performance
subroutine linkage
8
8 signed/unsigned single-cycle multiply
Pointers and stack operation optimized for C compiler
Uniform, linear address space (no register banks)
General-Purpose Hardware Peripherals
Two 16-bit timers with 8-bit prescalers supporting:
Timer mode
PWM mode
Capture/Compare mode
Parallel host interface, 8/16-bit selectable for use as a
communications coprocessor (IP2012 supports 8-bit
only)
External memory interface (IP2022 only)
One 8-bit timer with programmable 8-bit prescaler
One 8-bit real-time clock/counter with programmable
15-bit prescaler and 32 kHz crystal input
Watchdog timer with prescaler
10-bit, 8-channel ADC with 1/2 LSB accuracy
Analog comparator with hysteresis enable/disable
Brown-out minimum supply voltage detector
External interrupt inputs on 8 pins (Port B)
Sophisticated Power and Frequency/Clock
Management Support
Operating voltage of 2.3V to 2.7V (120 MHz)
Switching the system clock frequencies between dif-
ferent clock sources
On-chip PLL clock multiplier with pre- and post-divider
120 MHz on-chip clock from 4.8 MHz ext. crystal
160 MHz on-chip clock from 3.2 MHz ext. crystal
Changing the core clock using a selectable divider
Shutting down the PLL and/or the OSC input
Dynamic CPU speed control with
speed
instruction
Power-On-Reset (POR) logic
Flexible I/O
52 I/O Pins (48 on IP2012)
2.3V to 3.6V symmetric CMOS output drive (120MHz
part)
5V-tolerant inputs
Port A pins capable of sourcing/sinking 24 mA
Optional I/O synchronization to CPU core clock
Re-configurable Over The Internet
Customer application program updatable
Run-time self programming
On-chip in-system programming interface
On-chip in-system debugging support interface
Debugging at full IP2022 operating speed
Programming at device supply voltage level
Real-time emulation, program debugging, and inte-
grated software development environment offered by
leading third-party tool vendors
4
www.ubicom.com
IP2012 / IP2022 Data Sheet
1.2
Architecture
1.2.1
CPU
The IP2012 and IP2022 implement an enhanced Harvard
architecture (i.e. separate instruction and data memories)
with independent address and data buses. The 16-bit
program memory and 8-bit dual-port data memory allow
instruction fetch and data operations to occur in parallel.
The advantage of this architecture is that instruction fetch
and memory transfers can be overlapped by a multistage
pipeline, so that the next instruction can be fetched from
program memory while the current instruction is executed
with data from the data memory.
Ubicom has developed a revolutionary RISC-based
architecture that is deterministic, jitter free, and
completely reprogrammable.
The architecture implements a four-stage pipeline (fetch,
decode, execute, and write back). At the maximum
operating frequency of 160 MHz, instructions are
executed at the rate of one per 6.25 ns clock cycle.
1.2.2
Serializer/Deserializers
One of the key elements in optimizing the IP2012 and
IP2022 for device-to-device and device-to-human
communication is the inclusion of on-chip
serializer/deserializer units. Each unit supports popular
communication protocols such as GPSI, SPI, UART, USB,
and 10Base-T Ethernet, allowing the IP2000 series
devices to be used in bridge, access point and gateway
applications.
By performing data serialization and deserialization in
hardware, the CPU bandwidth needed to support serial
communications is greatly reduced, especially at high
baud rates. Providing two units (IP2022 only) allows easy
implementation of protocol conversion or bridging
functions between two fast serial devices, such as USB-
to-Ethernet, GPSI to ethernet, or Ethernet to Ethernet. A
single SerDes unit (IP2012) provides the ability to bridge
RS232, SPI, or WLAN (802.11b) to Ethernet.
1.2.3
Low-Power Support
Particular attention has been paid to minimizing power
consumption. For example, an on-chip PLL allows use of
a lower-frequency external source (e.g., an inexpensive
4.8MHz crystal can be used to produce a 120 MHz on-
chip clock; a 3.2 MHz crystal to produce a 160 MHz on-
chip clock), which reduces both power consumption and
EMI. In addition, software can change the execution
speed of the CPU to reduce power consumption, and a
mechanism is provided for automatically changing the
speed on entry and return from an interrupt service
routine. The
speed
instruction specifies power-saving
modes that include a clock divisor between 1 and 128.
This divisor only affects the clock to the CPU core, not the
timers. The
speed
instruction also specifies the clock
source (OSC1 clock, RTCLK oscillator, or PLL clock
multiplier), and whether to disable the OSC1 clock
oscillator or the PLL. The
speed
instruction executes
using the current clock divisor.
1.2.4
Memory
The IP2012 / IP2022 CPU executes from a 32K
16 flash
program memory and an 8K
16 RAM program/data
memory. In addition, the ability to write into the program
flash memory allows flexible non-volatile data storage. An
interface is available (IP2022 only) for up to 128K bytes of
linearly addressed external memory, which can be
expanded to 2M bytes with additional software-based I/O
addressing. At 120 MHz operation, the maximum
execution rate is 40 MIPS from flash memory and 120
MIPS from RAM. At 160 MHz operation, the maximum
execution rate is 53.33 MIPS from flash memory and 160
MIPS from RAM. Speed-critical routines can be copied
from the flash memory to the RAM for faster execution.
The IP2000 series devices have a mechanism for in-
system programming of their flash and RAM program
memories through a four-wire SPI interface, and software
has the ability to reprogram the program memories at run
time. This allows the functionality of a device to be
changed in the field over the Internet.
1.2.5
Instruction Set
The IP2000 series instruction set, using 16-bit words,
implements a rich set of arithmetic and logical operations,
including signed and unsigned 8-bit
8-bit integer
multiply with a 16-bit product.
PDF 
ZIP