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Электронный компонент: UT52L1664MC-6

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UTRON
UT52L1664/0864/0464
Rev. 1.4
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
UTRON TECHNOLOGY INC. P90006
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
REVISION HISTORY
REVISION DESCRIPTION DATE
Rev.1.0
Original
June 20, 2002
Rev.1.1
Revised
1. AC TIMING REQUIREMENTS
Input Pulse Levels:0.8V~2.0V 0.4V~2.4V
tIS(min):1, 1.5, 1.3, 2 2, 2.5, 2.5, 2.5ns
tIH(min):1, 0.8, 0.8, 0.8 1, 1, 1, 1ns
2. Output Load Condition
Jul. 09, 2002
Rev.1.2
Add Package Outline Dimension
Jul. 26, 2002
Rev.1.3
1. Page 1 : add access parameter into "Features"
ITEM -6
-7
-6
-7
Unit
t
CLK
(Min.) CL=2 -
-
10 10 ns
t
AC
(Max.) CL=2 -
-
6 6 ns
t
OH
(Min.) CL=2 -
-
3 3 ns
2. Page 34,35 : add 6ns,-7ns Limits parameters
Feb. 10, 2003
Rev.1.4
1. add Operating temperature :
Commercial : 0
~70
Extended : -20
~80
Apr. 25, 2003
UTRON
UT52L1664/0864/0464
Rev. 1.4
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM

UTRON TECHNOLOGY INC. P90006
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
DESCRIPTION
UT52L0464 is organized as 4-bank x 4,194,304-
word x 4-bit Synchronous DRAM with LVTTL
interface and UT52L0864 is organized as 4-bank x
2,097,152-word x 8-bit and UT52L1664 is
organized as 4-bank x 1,048,576-word x 16-bit. All
inputs and outputs are referenced to the rising
edge of CLK. UT52L0464, UT52L0864 and
UT52L1664 achieve very high speed data rates up
to 166MHz, and are suitable for main memories or
graphic memories in computer systems.

FEATURES
UT52L0464/0864/1664
ITEM
-6 -7 -7.5 -8
CL=2
10ns 10ns 10ns 10ns
tCLK Clock Cycle Time (Min.)
CL=3 6ns
7ns
7.5ns
8ns
tRAS Active to Precharge Command Preiod (Min.)
42ns
45ns
45ns
48ns
tRCD Row to Column Delay (Min.)
18ns 20ns 20ns 20ns
CL=2 6ns
6ns
6ns
6ns
tAC Access Time from CLK (Max.)
CL=3
5ns 5.4ns 5.4ns 6ns
tRC Ref/Active Command Period (Min.)
60ns
63ns
67.5ns
70ns
UT52L0464 85mA 85mA 85mA 85mA
UT52L0864
85mA 85mA 85mA 85mA
Icc1 Operation Current(Single Bank) (Max.)
UT52L1664
85mA 85mA 85mA 85mA
Icc6 Self Refresh Current(Max.)
-6,-7,-7.5,8
1mA
1mA
1mA
1mA

- Single 3.3V 0.3V power supply
- Operating temperature :
Commercial
:
0
~70
Extended : -20
~80
- Max. Clock frequency -6:166MHz<3-3-3>/-7:143MHz<3-3-3>/-7.5:133MHz<3-3-3>/-8:100MHz<2-2-2>
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- DQML and DQMU (UT52L1664)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 4096 refresh cycles /64ms
- LVTTL Interface
- Package
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
UTRON
UT52L1664/0864/0464
Rev. 1.4
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM

UTRON TECHNOLOGY INC. P90006
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
PIN CONFIGURATION(TOP VIEW)
PIN CONFIGURATION
(TOP VIEW)
400mil 54pin TSOP(II)
Vss
DQ15
VssQ
DQ13
VddQ
NC
DQ11
VssQ
DQ9
VddQ
Vss
DQMU
CLK
CKE
A9
A8
A7
A6
A5
NC
A11
DQ14
DQ12
DQ10
DQ8
Vss
A4
Vdd
DQ0
VddQ
DQ2
VssQ
DQ4
VddQ
DQ6
VssQ
/WE
/RAS
DQML
/CAS
Vdd
BA0(A13)
/CS
A10(AP)
A0
A1
A2
DQ1
DQ3
DQ5
DQ7
BA1(A12)
Vdd
A3
Vdd
DQ0
VddQ
DQ1
VssQ
DQ2
VddQ
DQ3
VssQ
/WE
/RAS
NC
/CAS
Vdd
BA0(A13)
/CS
A10(AP)
A0
A1
A2
NC
NC
NC
NC
BA1(A12)
Vdd
A3
Vdd
NC
VddQ
DQ0
VssQ
NC
VddQ
DQ1
VssQ
/WE
/RAS
NC
/CAS
Vdd
BA0(A13)
/CS
A10(AP)
A0
A1
A2
NC
NC
NC
NC
BA1(A12)
Vdd
A3
10
11
12
13
14
15
16
17
18
19
20
25
24
23
22
21
1
2
3
4
5
6
7
8
9
26
27
40
39
38
37
36
35
34
33
32
31
30
29
28
50
49
48
47
46
45
44
43
42
41
51
52
53
54
Vss
NC
VssQ
DQ3
VddQ
NC
NC
VssQ
DQ2
VddQ
Vss
DQM
CLK
CKE
A9
A8
A7
A6
A5
NC
A11
NC
NC
NC
NC
Vss
A4
UT52L1664
UT52L0864
UT52L0464
A4
Vss
DQ7
VssQ
DQ6
VddQ
NC
DQ5
VssQ
DQ4
VddQ
Vss
DQM
CLK
CKE
A9
A8
A7
A6
A5
NC
A11
NC
NC
NC
NC
Vss
UTRON
UT52L1664/0864/0464
Rev. 1.4
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM

UTRON TECHNOLOGY INC. P90006
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
CLK
Master Clock
CKE
Clock Enable
/CS
Chip Select
/RAS
Row Address Strobe
/CAS
Column Address Strobe
/WE
Write Enable
DQ0-15
Data I/O
DQM
Output Disable / Write Mask
A0-11
Address Input
BA0,1
Bank Address
Vdd
Power Supply
VddQ
Power Supply for Output
Vss
Ground
VssQ
Ground for Output
UTRON
UT52L1664/0864/0464
Rev. 1.4
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM

UTRON TECHNOLOGY INC. P90006
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
BLOCK DIAGRAM
I/O Buffer
Memory Array
4096 X 512 X 8
Cell Array
Bank #0
Memory Array
4096 X 512 X 8
Cell Array
Bank #1
Memory Array
4096 X 512 X 8
Cell Array
Bank #2
Memory Array
4096 X 512 X 8
Cell Array
Bank #3
Mode
Register
Control Circuitry
Address Buffer
Control Signal Buffer
Clock Buffer
DQ0-7
A0-11
BA0,1
CLK
CKE
/CS
/RAS
/CAS /WE
DQM

Note
This figure shows the UT52L0864
The UT52L0464 configuration is 4096x1024x4 of cell array and DQ0-3
The UT52L1664 configuration is 4096x256x16 of cell array and DQ0-15