UTRON

UT61512

Rev 1.2

64K X 8 BIT HIGH SPEED CMOS SRAM

_____________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80021
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919

FEATURES

Fast access time : 8/12/15 ns (max.)

Low operating power consumption :

100 mA (typical)

Single 5V power supply
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Package : 32-pin 300 mil SOJ

32-pin 8x20mm TSOP-I

FUNCTIONAL BLOCK DIAGRAM

MEMORY ARRAY

512 ROWS X 1024 COLUMNS

COLUMN I/O

COLUMN DECODER

I/O

CONTROL

LOGIC

CONTROL

I/O1

VSS

VCC

CE1

I/O8

.
.

. .

A11 A9 A3 A2

.
.
.

A10

ROW

DECODER

A15

A13

A14

A12

A7
A6

A5
A4

PIN DESCRIPTION

SYMBOL DESCRIPTION
A0 - A15

Address Inputs

I/O1 - I/O8

Data Inputs/Outputs

CE1

Chip Enable 1 input

CE2

Chip Enable 2 input

Write Enable Input

Output Enable Input

Power

Supply

Ground

NC No

Connection

GENERAL DESCRIPTION

The UT61512 is a 524,288-bit high-speed
CMOS static random access memory
organized as 655,036 words by 8 bits. It is
fabricated using high performance, high
reliability CMOS technology.

The UT61512 is designed for high-speed
system applications. It is particularly suited
for use in high-density high-speed system
applications.

The UT61512 operates from a single 5V
power supply and all inputs and outputs are
fully TTL compatible.

PIN CONFIGURATION

SOJ

A12

A7
A6

I/O1

I/O2

CE2

A11

A10

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

Vss

UT61512

A13

A14

Vcc

A15

A11

A13

I/O3

A10

A14

A12

Vcc

I/O8

I/O7

I/O6

I/O5

Vss

I/O2

I/O1

UT61512

CE2

A15

I/O4

TSOP-I

UTRON

UT61512

Rev 1.2

64K X 8 BIT HIGH SPEED CMOS SRAM

ABSOLUTE MAXIMUM RATINGS*

PARAMETER

SYMBOL

RATING

UNIT

Terminal Voltage with Respect to Vss

TERM

-0.5 to +6.5

Operating Temperature

0 to +70

Storage Temperature

STG

-65 to +150

Power Dissipation

DC Output Current

OUT

Soldering Temperature (under 10 sec)

Tsolder

260

*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for
extended period may affect device reliability.

TRUTH TABLE

MODE

CE2

I/O OPERATION

SUPPLY CURRENT

Standby

High - Z

SB1

Standby

High -Z

SB1

Output Disable

High - Z

Read

OUT

Write

Note: H = V

, L=V

, X = Don't care.

DC ELECTRICAL CHARACTERISTICS (V

= 5.0V

�

10%, T

= 0

to 70

)

PARAMETER

SYMBOL TEST CONDITION

MIN. MAX. UNIT

Input High Voltage

2.2

+0.5 V

Input Low Voltage

- 0.5

0.8

Input Leakage Current

- 1

�A

Output Leakage Current

I/O

CE1 = V

CE2 =

or OE = V

= V

- 1

�A

Output High Voltage

= - 4mA

2.4

Output Low Voltage

= 8mA

0.4

Operating Power

CE1 = V

IL ,

CE2 =

- 8 -

190

Supply Current

I/O

0mA , Cycle=Min.

- 12 -

160

- 15 -

140

Standby Power

CE1 = V

IH or

CE2 =

Supply Current

SB1

CE1

-0.2V or

CE2

0.2V

Notes:
1. Overshoot : Vcc+2.0v for pulse width less than 6ns.
2. Undershoot : Vss-2.0v for pulse width less than 6ns.
3. Overshoot and Undershoot are sampled, not 100% tested.

UTRON

UT61512

Rev 1.2

64K X 8 BIT HIGH SPEED CMOS RAM

CAPACITANCE (T

=25

, f=1.0MHz)

PARAMETER

SYMBOL MIN.

MAX.

UNIT

Input Capacitance

Input/Output Capacitance

I/O

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels

0V to 3.0V

Input Rise and Fall Times

3ns

Input and Output Timing Reference Levels

1.5V

Output Load

=30pF, I

=-4mA/8mA

AC ELECTRICAL CHARACTERISTICS (V

= 5V

�

10% , T

= 0

to 70

)

(1) READ CYCLE

PARAMETER

SYMBOL

UT61512-8

UT61512-12 UT61512-15 UNIT

MIN. MAX. MIN. MAX. MIN. MAX.

Read Cycle Time

8 - 12 - 15 - ns

Address Access Time

8 - 12 - 15 ns

Chip Enable Access Time

ACE

8 - 12 - 15 ns

Output Enable Access Time

4 - 6 - 7 ns

Chip Enable to Output in Low Z

CLZ*

2 - 3 - 4 - ns

Output Enable to Output in Low Z

OLZ*

0 - 0 - 0 - ns

Chip Disable to Output in High Z

CHZ*

- 4 - 6 - 7 ns

Output Disable to Output in High Z

OHZ*

4 - 6 - 7 ns

Output Hold from Address Change

3 - 3 - 3 - ns

(2) WRITE CYCLE
PARAMETER

SYMBOL UT61512-8 UT61512-12 UT61512-15 UNIT

MIN. MAX. MIN. MAX. MIN. MAX.

Write Cycle Time

8 - 12 - 15 - ns

Address Valid to End of Write

6.5 - 10 - 12 - ns

Chip Enable to End of Write

6.5 - 10 - 12 - ns

Address Set-up Time

0 - 0 - 0 - ns

Write Pulse Width

6.5 - 9 - 10 - ns

Write Recovery Time

0 - 0 - 0 - ns

Data to Write Time Overlap

4 - 6 - 7 - ns

Data Hold from End of Write Time

0 - 0 - 0 - ns

Output Active from End of Write

OW*

1.5 - 3 - 4 - ns

Write to Output in High Z

WHZ*

4 - 6 - 7 ns

*These parameters are guaranteed by device characterization, but not production tested.

UTRON

UT61512

Rev 1.2

64K X 8 BIT HIGH SPEED CMOS RAM

TIMING WAVEFORMS

READ CYCLE 1

(Address Controlled)

(1,2,4)

Address

DOUT

Data Valid

READ CYCLE 2

(

and

Controlled)

(1,3,5,6)

Notes :
1. WE is HIGH for read cycle.
2. Device is continuously selected CE =V

IL.

3. Address must be valid prior to or coincident with CE transition; otherwise t

is the limiting parameter.

4. OE is LOW.
5. t

CLZ

, t

OLZ

, t

CHZ

and t

OHZ

are specified with C

= 5pF. Transition is measured

�

500mV from steady state.

6. At any given temperature and voltage condition, t

CHZ

is less than t

CLZ

, t

OHZ

is less than t

OLZ.

ACE1

ACE2

OLZ

CLZ1

CLZ2

High-Z

CHZ1

CHZ2

OHZ

Data Valid

High-Z

Address

CE1

CE2

DOUT

UTRON

UT61512

Rev 1.2

64K X 8 BIT HIGH SPEED CMOS RAM

WRITE CYCLE 1

(

Controlled)

(1,2,3,5)

Address

OUT

High-Z

Data Valid

CE2

CW2

CW1

WHZ

(4)

WRITE CYCLE 2

(

Controlled)

(1,2,5)

Address

OUT

High-Z

(4)

Data Valid

CE2

CW1

CW2

WHZ

Notes :
1. WE or CE must be HIGH during all address transitions.

2. A write occurs during the overlap of a low CE and a low WE .

3. During a WE controlled with write cycle with OE LOW, t

must be greater than t

WHZ

to allow the drivers

to turn off and data to be placed on the bus.

4. During this period, I/O pins are in the output state, and input singals must not be applied.
5. If

the CE LOW transition occurs simultaneously with or after WE LOW transition, the outputs remain in a high

impedance state.
6. t

and t

WHZ

are specified with C

= 5pF. Transition is measured

�

500mV from steady state.

Электронный компонент: UT61512JC-15