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Электронный компонент: UT6164C

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UTRON
UT6164C
Rev. 1.1
8K X 8 BIT HIGH SPEED CMOS SRAM

UTRON TECHNOLOGY INC.
P80074
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
REVISION HISTORY
REVISION DESCRIPTION DATE
Rev. 1.0
Original
Oct 15,2001
Rev. 1.1
1. Revised Page 8 : 28 STSOP DIMENSION :
a. Db D,
b. D HD
Jan 20,2003
UTRON
UT6164C
Rev. 1.1
8K X 8 BIT HIGH SPEED CMOS SRAM

UTRON TECHNOLOGY INC. P80074
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
FEATURES
Fast access time : 10/12/15 ns (max.)
Low operating power consumption :
80 mA (typical)
Single 5V power supply
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Package : 28-pin 300 mil SOJ
28-pin 8mm13.4mm STSOP

FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
128
512
MEMORY
ARRAY
COLUMN I/O
OE
WE
A0-A12
Vcc
Vss
I/O1-I/O8
CE1
CE2


PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A12
Address Inputs
I/O1 - I/O8
Data Inputs/Outputs
1
CE
CE2
Chip Enable Input
WE
Write Enable Input
OE
Output Enable Input
V
CC
Power
Supply
V
SS
Ground




GENERAL DESCRIPTION

The UT6164C is a 65,536-bit high-speed CMOS
static random access memory organized as 8,192
words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.

The UT6164C is designed for high-speed system
applications. It is particularly suited for use in
high-density high-speed system applications.

The UT6164C operates from a single 5V power
supply and all inputs and outputs are fully TTL
compatible.
PIN CONFIGURATION
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
Vcc
A8
A9
A11
A10
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
UT6164C
SOJ
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
WE
OE
CE2
NC
CE1
I/O4
A11
A9
A8
CE2
I/O3
A10
NC
A12
A7
A6
A5
Vcc
I/O8
I/O7
I/O6
I/O5
Vss
I/O2
I/O1
A0
A1
A2
A4
A3
UT6164C
STSOP
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
WE
OE
CE1
UTRON
UT6164C
Rev. 1.1
8K X 8 BIT HIGH SPEED CMOS SRAM

UTRON TECHNOLOGY INC.
P80074
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
SYMBOL
RATING
UNIT
Terminal Voltage with Respect to Vss
V
TERM
-0.5 to +6.5
V
Operating Temperature
T
A
0 to +70
Storage Temperature
T
STG
-65 to +150
Power Dissipation
P
D
1
W
DC Output Current
I
OUT
50
mA
Soldering Temperature (under 10 sec)
Tsolder
260
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may
affect device reliability.
TRUTH TABLE
MODE
1
CE
CE2 OE
WE
I/O OPERATION
SUPPLY CURRENT
Standby
H
X
X
X
High - Z
I
SB
,
I
SB1
Standby
X
L
X
X
High - Z
I
SB
,
I
SB1
Output Disable
L
H
H
H
High - Z
I
CC
Read L
H
L
H
D
OUT
I
CC
Write L
H
X
L
D
IN
I
CC
Note: H = V
IH
, L=V
IL
, X = Don't care.

DC ELECTRICAL CHARACTERISTICS
(V
CC
= 5V
10%, T
A
= 0
to 70
)
PARAMETER
SYMBOL TEST CONDITION
MIN.
MAX.
UNIT
Input High Voltage
V
IH
2.2
V
CC
+0.5 V
Input Low Voltage
V
IL
-
0.5
0.8
V
Input Leakage Current
I
LI
V
SS
V
IN
V
CC
- 1
1
A
Output Leakage Current
I
LO
V
SS
V
I/O
V
CC
1
CE =V
IH
or CE2=V
IL
or
OE =V
IH
or
WE
=V
IL
- 1
1
A
Output High Voltage
V
OH
I
OH
= - 4mA
2.4
-
V
Output Low Voltage
V
OL
I
OL
= 8mA
-
0.4
V
- 10
-
180
mA
- 12
-
160
mA
Operating Power
Supply Current
I
CC
Cycle time=Min.
1
CE
= V
IL ,
CE2= V
IH
I
I/O
=
0mA
- 15
-
140
mA
Standby Current (TTL)
I
SB
1
CE = V
IH
or
CE2= V
IL
-
30
mA
Standby Current (CMOS)
I
SB1
1
CE
V
CC
-0.2V or CE2
0.2V
- 5
mA
Notes:
1. Overshoot : Vcc+2.0v for pulse width less than 8ns.
2. Undershoot : Vss-2.0v for pulse width less than 8ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON
UT6164C
Rev. 1.1
8K X 8 BIT HIGH SPEED CMOS SRAM

UTRON TECHNOLOGY INC. P80074
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
CAPACITANCE (T
A
=25 , f=1.0MHz)

PARAMETER
SYMBOL MIN.
MAX.
UNIT
Input Capacitance
C
IN
-
8
pF
Input/Output Capacitance
C
I/O
-
10
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS

Input Pulse Levels
0V to 3.0V
Input Rise and Fall Times
3ns
Input and Output Timing Reference Levels
1.5V
Output Load
C
L
=30pF, I
OH
/I
OL
=-4mA/8mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5V
10% , T
A
= 0
to 70
)
(1) READ CYCLE
UT6164C-10 UT6164C-12 UT6164C-15 UNIT
PARAMETER
SYMBOL
MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time
t
RC
10
- 12 - 15 - ns
Address Access Time
t
AA
-
10 - 12 - 15
ns
Chip Enable Access Time
t
ACE
-
10 - 12 - 15
ns
Output Enable Access Time
t
OE
-
5 - 6 - 7
ns
Chip Enable to Output in Low Z
t
CLZ*
2
- 3 - 4 - ns
Output Enable to Output in Low Z
t
OLZ*
0
- 0 - 0 - ns
Chip Disable to Output in High Z
t
CHZ*
-
5 - 6 - 7
ns
Output Disable to Output in High Z
t
OHZ*
-
5 - 6 - 7
ns
Output Hold from Address Change
t
OH
3
- 3 - 3 - ns
(2) WRITE CYCLE
UT6164C-10 UT6164C-12 UT6164C-15
UNIT
PARAMETER SYMBOL
MIN. MAX. MIN. MAX. MIN. MAX.
Write Cycle Time
t
WC
10
- 12 - 15 - ns
Address Valid to End of Write
t
AW
8
- 10 - 12 - ns
Chip Enable to End of Write
t
CW
8
- 10 - 12 - ns
Address Set-up Time
t
AS
0
- 0 - 0 - ns
Write Pulse Width
t
WP
8
- 9 - 10 - ns
Write Recovery Time
t
WR
0
- 0 - 0 - ns
Data to Write Time Overlap
t
DW
6
- 7 - 8 - ns
Data Hold from End of Write Time
t
DH
0
- 0 - 0 - ns
Output Active from End of Write
t
OW*
2
- 3 - 4 - ns
Write to Output in High Z
t
WHZ*
- 6 - 7 - 8
ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON
UT6164C
Rev. 1.1
8K X 8 BIT HIGH SPEED CMOS SRAM

UTRON TECHNOLOGY INC. P80074
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
(1,2,4)
t
RC
Address
DOUT
Data Valid
t
AA
t
OH
t
OH

READ CYCLE 2
(
1
CE
CE2
and
OE
Controlled)
(1,3,5,6)
t
RC
t
AA
t
ACE1
t
ACE2
t
OE
t
CHZ1
t
CHZ2
t
OHZ
t
CLZ1
t
CLZ2
t
OH
t
OLZ
HIGH-Z
Data Valid
HIGH-Z
Address
CE1
CE2
OE
Dout

Notes :
1.
WE
is high for read cycle.
2. Device is continuously selected
1
CE
=V
IL
and CE2=V
IH.
3. Address must be valid prior to or coincident with
1
CE
and CE2 transition; otherwise t
AA
is the limiting parameter.
4.
OE
is low.
5. t
CLZ1
, t
CLZ2
, t
OLZ
, t
CHZ1
, t
CHZ2
and t
OHZ
are specified with C
L
=5pF. Transition is measured
500mV from steady
state.
6. At any given temperature and voltage condition, t
CHZ1
is less than t
CLZ1
, t
CHZ2
is less than t
CLZ2
, t
OHZ
is less than
t
OLZ.