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Электронный компонент: UT6164C64AQ-5

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UTRON
UT6164C64A
Rev 1.1
64K X 64 SYNCHRONOUS PIPELINED BURST CMOS SRAM
_______________________________________________________________________________________________

UTRON TECHNOLOGY INC. P80003
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
FEATURES
Single 3.3V -5% and +10% power supply
Support 2.5V I/O
Fast clock access time:
5ns /100MHz, 6ns /75MHz, 7ns /66Mhz
2 clocks chip enable/1 clock chip disable
operation
5V-tolerant inputs, TTL/LVTTL compatible
outputs

GENERAL DESCRIPTION
Synchronous pipeline operation
Internally self-timed WRITE cycle
BYTE WRITE and GLOBAL WRITE
control
WRITE pass-through capability
Burst control pin (interleaved or linear
burst)
ZZ snooze mode control
128-pin PQFP and TQFP package

The UT6164C64A is a 4,194,304-bit synchronous pipelined burst CMOS SRAM organized as
65,536 words by 64 bits. It is fabricated with high performance and high reliability CMOS
technology.

The UT6164C64A integrates 65,536 x 64 SRAM cells with advanced synchronous peripheral
circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs
include addresses, data inputs, address-pipelining chip enable (CE#), burst control inputs
(ADSC#, ADSP#, and ADV#), write enables (BW1#, BW2#, BW3#, BW4#, BW5#, BW6#,
BW7#, BW8# and BWE#), and global write (GW#). Asynchronous inputs include the output
enable (OE#). The data outputs (I/O), enabled by OE#, are also asynchronous. Addresses
and chip enables are registered with either address status processor (ADSP#) or address
status controller (ADSC#) input pins. Subsequent burst addresses can be internally
generated as controlled by the burst advance pin (ADV#). Address, data inputs, and wire
controls are registered on-chip to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs. Individual byte write allows
individual byte to be written. BW1# controls I/O1-I/O8. BW2# controls I/O9-I/O16. BW3#
controls I/O17-I/O24. BW4# controls I/O25-I/O32. BW5# controls I/O33-I/O40. BW6# controls
I/O41-I/O48. BW7# controls I/O49-I/O56. BW8# controls I/O57-I/O64. BW1#, BW2#, BW3#,
BW4#, BW5#, BW6#, BW7# and BW8# can be active only with BWE# being LOW. GW#
being LOW causes all bytes to be written. WRITE pass-through capability allows written data
available at the output for the immediately next READ cycle. This device also incorporates
pipelined enable circuit for easy depth expansion without penalizing system performance.

The UT6164C64A operates from a +3.3V power supply. All inputs and outputs are TTL-
compatible. The devise is ideally suited for 486, Pentium
TM
, 680X0, and PowerPC systems
and for systems that are benefited from a wide synchronous data bus.
UTRON
UT6164C64A
Rev 1.1
64K X 64 SYNCHRONOUS PIPELINED BURST CMOS SRAM
_______________________________________________________________________________________________

UTRON TECHNOLOGY INC. P80003
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2

FUNCTIONAL BLOCK DIAGRAM































Address
Register
64K X 64
Memory Array
Burst
Address
Counter
A`0 - A'1
A0 - A1
A0 - A15
A2 - A15
Clock
Control
Chip Enable
Control
Control
Logic
Data In
Register
Output
Register
Buffer
CLK
ADSP#
ADSC#
ADV#
OE#
GW#
Byte
Write
Control
BWE#
BW1#-BW8#
V
CC
V
SS
I/O1 - I/O64
CE1#
CE2
CE3#
ZZ
VccQ
VssQ
MODE
UTRON
UT6164C64A
Rev 1.1
64K X 64 SYNCHRONOUS PIPELINED BURST CMOS SRAM
____________________________________________________________________________________________________________
____________________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80003
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
PIN CONFIGURATION
UT6164C64A
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
I/O18
VCCQ
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
VSSQ
96
95
VSSQ
I/O26
I/O25
I/O24
I/O23
I/O22
VSSQ
I/O20
I/O19
I/O21
VCCQ
I/O27
97
99
98
102
101
100
I/O31
I/O30
I/O32
VCCQ
I/O29
I/O28
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
58
59
60
61
62
63
64
VC
C
A3
A4
A5
A6
A7
NC
A8
A9
A10
A11
A12
VSS
VC
C
A13
A14
A15
MO
DE
NC
VSS
Q
ZZ
VC
C
Q
VSS
A2
A1
A0
VSSQ
VCCQ
VCCQ
I/O39
I/O40
I/O41
I/O42
I/O43
VCCQ
I/O45
I/O46
VSSQ
VSSQ
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
I/O47
I/O48
I/O49
I/O50
I/O51
I/O52
I/O53
I/O54
I/O55
I/O56
I/O57
I/O58
I/O59
I/O60
I/O61
I/O62
I/O63
I/O64
7
8
I/O44
I/O38
6
4
5
1
2
3
I/O34
I/O35
I/O33
I/O36
I/O37
11
0
11
1
11
2
11
3
11
4
11
5
11
6
11
7
11
8
11
9
12
0
12
1
12
2
12
3
12
4
12
5
12
6
12
7
12
8
10
9
10
8
10
7
10
6
10
5
10
4
10
3
VC
C
VSS
BW3#
BW4#
GW
#
BWE
#
CL
K
OE
#
BW5#
BW6#
BW7#
BW8#
CE
1
#
VC
C
VSS
CE
3
#
NC
CE
2
NC
VC
C
Q
AD
V#
VSS
Q
BW2#
BW1#
AD
SC
#
AD
SP
#




UTRON
UT6164C64A
Rev 1.1
64K X 64 SYNCHRONOUS PIPELINED BURST CMOS SRAM
____________________________________________________________________________________________________________
____________________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80003
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4

PIN DESCRIPTION
PIN NO.
SYMBOL
DESCRIPTION
42-44, 47-51,
53-57, 60-62
A0 - A15
Address Inputs
115 CLK
Clock
105
ADSP#
Address Status Processor
106
ADSC#
Address Status Control
104 ADV#
Address
Advance
121, 126, 124
CE1#,
CE2,
CE3#
Chip Enable
116 OE#
Output
Enable
113
GW#
Global Write
114, 107-108,
111-112,
117-120
BWE#,
BW1# -
BW8#
Byte Write Enable
41 MODE
Burst
Mode
63 ZZ
Snooze
66-76, 79-88,
91-101, 2-12,
15-24, 27-37
I/O1-I/O64 Data
Inputs/Outputs
45, 58, 109,
122
VCC Power
Supply
46, 59, 110,
123
VSS Ground
13, 25, 38, 64,
77, 89, 102,
128
VCCQ
Output Buffer Supply (For 2.5V I/O : 2.4V to VCC)
1, 14, 26, 39,
65, 78, 90, 103
VSSQ
Output Buffer Ground
40, 52, 125,
127
NC No
Connection
UTRON
UT6164C64A
Rev 1.1
64K X 64 SYNCHRONOUS PIPELINED BURST CMOS SRAM
_______________________________________________________________________________________________

UTRON TECHNOLOGY INC. P80003
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
TRUTH TABLE
OPERATION ADDRESS
USED
CE1# CE2 CE3# ADSP#
ADSC#
ADV# WRITE# OE# CLK I/O
Deselected
Cycle.
Power
Down
None H X X X L X X X L-H
High-Z
Deselected
Cycle.
Power
Down
None L L X L X X X X L-H
High-Z
Deselected
Cycle.
Power
Down
None L X H L X X X X L-H
High-Z
Deselected Cycle. Power Down None
L
L
X
H
L
X
X
X
L-H
High-Z
Deselected Cycle. Power Down None
L
X
H
H
L
X
X
X
L-H
High-Z
READ Cycle. Begin Burst
External
L
H
L
L
X
X
X
L
L-H
Q
READ Cycle. Begin Burst
External
L
H
L
L
X
X
X
H
L-H
High-Z
WRITE
Cycle.
Begin
Burst External
L H L H L X L X L-H
D
READ Cycle. Begin Burst
External
L
H
L
H
L
X
H
L
L-H
Q
READ Cycle. Begin Burst
External
L
H
L
H
L
X
H
H
L-H
High-Z
READ Cycle. Continue Burst
Next
X
X
X
H
H
L
H
L
L-H
Q
READ Cycle. Continue Burst
Next
X
X
X
H
H
L
H
H
L-H
High-Z
READ Cycle. Continue Burst
Next
H
X
X
X
H
L
H
L
L-H
Q
READ Cycle. Continue Burst
Next
H
X
X
X
H
L
H
H
L-H
High-Z
WRITE Cycle. Continue Burst
Next
X
X
X
H
H
L
L
X
L-H
D
WRITE Cycle. Continue Burst
Next
H
X
X
X
H
L
L
X
L-H
D
READ Cycle. Suspend Burst
Current
X
X
X
H
H
H
H
L
L-H
Q
READ Cycle. Suspend Burst
Current
X
X
X
H
H
H
H
H
L-H
High-Z
READ
Cycle.
Suspend
Burst
Current
H X X X H H H L L-H
Q
READ
Cycle.
Suspend
Burst
Current
H X X X H H H H L-H
High-Z
WRITE Cycle. Suspend Burst
Current
X
X
X
H
H
H
L
X
L-H
D
WRITE Cycle. Suspend Burst
Current
H
X
X
X
H
H
L
X
L-H
D

Note: 1.X means "don't care." H means logic HIGH. L means logic LOW. WRITE = L means [BWE# + BW1# * BW2# *
BW3# * BW4# * BW5# * BW6# * BW7# * BW8#] * GW# equals LOW. WRITE = H means [BWE# + BW1# * BW2# *
BW3# * BW4# * BW5# * BW6# * BW7# * BW8#] * GW# equals HIGH.
2. BW1# enables write to I/O1-I/O8. BW2# enables write to I/O9-I/O16. BW3# enables write to I/O17-I/O24.
BW4# enables write to I/O25-I/O32. BW5# enables write to I/O33-I/O40. BW6# enables write to I/O41-I/O48. BW7#
enables write to I/O49-I/O56. BW8# enables write to I/O57-I/O64.
3. All inputs except OE# must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
4. Suspending burst generates wait cycle.
5. For a write operation following a read operation. OE# must be high before the input data required setup time
plus High-Z time for OE# and staying HIGH throughout the input data hold time.
6. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
7. ADSP# LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE
cycle can be performed by setting WRITE LOW for the CLK L-H edge of the subsequent wait cycle. Refer to
WRITE timing diagram for clarification.


PARTIAL TRUTH TABLE FOR WRITE
FUNCTION
GW#
BWE#
BW1#
BW2# BW3# BW4# BW5# BW6# BW7# BW8#
READ
H H X X X X X X X X
READ
H L H H H H H H H H
WRITE
one
byte
H L L H H H H H H H
WRITE
all
bytes
H L L L L L L L L L
WRITE
all
bytes
L X X X X X X X X X




UTRON
UT6164C64A
Rev 1.1
64K X 64 SYNCHRONOUS PIPELINED BURST CMOS SRAM
____________________________________________________________________________________________________________
____________________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80003
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
6
INTERLEAVED BURST ADDRESS TABLE (MODE=NC/Vcc)
FIRST ADDRESS
(EXTERNAL)
SECOND ADDRESS
(INTERNAL)
THIRD ADDRESS
(INTERNAL)
FOURTH ADDRESS
(INTERNAL)
A...A00 A...A01
A...A10
A...A11
A...A01 A...A00
A...A11
A...A10
A...A10 A...A11
A...A00
A...A01
A...A11 A...A10
A...A01
A...A00

LINEAR BURST ADDERSS TABLE (MODE=GND)
FIRST ADDRESS
(EXTERNAL)
SECOND ADDRESS
(INTERNAL)
THIRD ADDRESS
(INTERNAL)
FOURTH ADDRESS
(INTERNAL)
A...A00 A...A01
A...A10 A...A11
A...A01 A...A10
A...A11 A...A00
A...A10 A...A11
A...A00 A...A01
A...A11 A...A00
A...A01 A...A10

PASS-THROUGH TRUTH TABLE
PREVIOUS CYCLE
PRESENT CYCLE
NEXT CYCLE
OPERATION BWN#
OPERATION
CE# BWN# OE# OPERATION
Initiate WRITE cycle, all bytes
Address=A(n-1). data=D(n-1)
All L
2, 3
READ cycle. Register A(n).
Q=D(n-1)
L H L Read
D(n)
Initiate WRITE cycle, all bytes
Address=A(n-1). data=D(n-1)
All L
2, 3
READ cycle. Register A(n).
Q=HIGH-Z
L H H
Read
D(n)
Initiate WRITE cycle, one byte
Address=A(n-1). data=D(n-1)
One L
2, 3
READ cycle. Register A(n).
Q=D(n-1) for one byte
L H L Read
D(n)
Initiate WRITE cycle, all bytes
Address=A(n-1). data=D(n-1)
All L
2
Deselect
cycle
Q=HIGH-Z
H
X
X
No carry-over from
previous cycle
Note: 1. Previous cycle may be any cycle (non-burst, burst, or wait) and next cycle is read cycle (non-burst, burst, or wait).
2. BWE# is LOW for individual byte WRITE.
3. GW# LOW yields the same result for all-byte WRITE operation.

ABSOLUTE MAXIMUM RATINGS
*
PARAMETER
RATING
UNIT
Voltage on V
CC
Supply Relative to V
SS
-0.5 to +4.6
V
V
IN
-0.5 to +6
V
Storage Temperature (plastic)
-55 to +150
Junction Temperature
+150
Power Dissipation
1.6
W
Short Circuit Output Current
100
mA
*Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for
extended periods may affect device reliability.



UTRON
UT6164C64A
Rev 1.1
64K X 64 SYNCHRONOUS PIPELINED BURST CMOS SRAM
____________________________________________________________________________________________________________
____________________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80003
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
7
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 3.3V -5% and +10%, T
A
= 0 to 70)
PARAMETER
SYMBOL TEST CONDITION
MIN.
MAX.
UNIT
NOTES
Input High (Logic 1) Voltage
V
IH
2.0
5.5
V
1, 2
Input Low (Logic 0) Voltage
V
IL
- 0.3
0.8
V
1, 2
Input Leakage Current
IL
I
0V
V
IN
V
CC
- 1
1
A
14
Output Leakage Current
IL
O
Output(s)
disabled.
0V V
OUT
V
CC
- 1
1
A
Output High Voltage (3.3V I/O)
V
OH
I
OH
= - 4mA
2.4
-
V
1, 11
Output Low Voltage
V
OL
I
OL
= 8mA
-
0.4
V
1, 11
Supply Voltage
V
CC
3.1
3.6
V
1
I/O Supply Voltage (3.3V I/O)
V
CC
Q
3.1
3.6
V
1
I/O Supply Voltage (2.5V I/O)
V
CC
Q
2.4
3.6
V
1

DESCRIPTION
CONDITIONS
SYM TYP -5ns -6ns -7ns UNIT
NOTES
Power Supply
Current Operating
Device selected: all inputs V
IL
or
V
IH
cycle time t
KC
MIN; V
CC
=MAX;
outputs open
I
CC
180 360 315 270 mA 3,
12,
13
Power Supply
Current Idle
Device selected: ADSC#, ADSP#, ADV#,
GW#, BWE# V
IH
, all other inputs V
IL
or V
IH
V
CC
=MAX;
cycle time t
KC
MIN; outputs open
I
SB1
30 60 55 50 mA
12,
13
CMOS Standby
Device selected: V
CC
=MAX;
all inputs V
SS
+0.2 or V
CC
-0.2;
all inputs static; CLK frequency = 0
I
SB2
2 20 20 20 mA
12,
13
TTL Standby
Device selected: all inputs V
IL
or
V
IH
all inputs static; V
CC
=MAX;
CLK frequency = 0
I
SB3
15 40 40 40 mA
12,
13
Clock Running
Device selected:
all inputs V
IL
or V
IH
; V
CC
=MAX;
CLK cycle time t
KC
MIN
I
SB4
30 60 55 50 mA
12,
13
Power-Down
Mode Current
ZZ Vcc - 0.2
I
ZZ
1 10 10 10 mA
12,
13


CAPACITANCE
(T
A
= 25, f = 1MHz)
PARAMETER
SYMBOL
TYP.
MAX.
UNIT
NOTES
Input Capacitance
C
IN
3
4
pF
4
Input/Output Capacitance
C
I/O
6
7
pF
4










UTRON
UT6164C64A
Rev 1.1
64K X 64 SYNCHRONOUS PIPELINED BURST CMOS SRAM
____________________________________________________________________________________________________________
____________________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80003
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
8
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V -5% and +10%, TA = 0 to 70)
PARAMETER
-5
-6
-7
SYM
MIN MAX MIN MAX MIN MAX UNITS
NOTES
Clock
Clock cycle time
t
KC
10
- 12
- 15
- ns
-
Clock HIGH time
t
KH
4
- 4
- 5
- ns
-
Clock LOW time
t
KL
4
- 4
- 5
- ns
-
Output Times
Clock to output valid
t
KO
-
5 -
6 -
7
ns -
Clock to output invalid
t
KOX
2
- 2
- 2
- ns
-
Clock to output in Low-Z
t
KOZ
3
- 3
- 3
- ns 6,
7
Clock to output in High-Z
t
KOHZ
-
5 -
5 -
6
ns
6,
7
OE# to output valid
t
OEO
-
5 -
5 -
5
ns
9
OE# to output in Low-Z
t
OELZ
0
- 0
- 0
- ns 6,
7
OE# to output in High-Z
t
OEHZ
-
4 -
5 -
6
ns
6,
7
Setup Times
Address setup
t
AS
2.2
- 2.5
- 2.5
- ns 10
Address status setup
t
ADSS
2.2
- 2.5
- 2.5
- ns 10
Address advance setup
t
ADVS
2.2
- 2.5
- 2.5
- ns 10
Write setup
t
WS
2.2
- 2.5
- 2.5
- ns 10
Data setup
t
DS
2.2
- 2.5
- 2.5
- ns 10
Chip enable setup
t
CES
2.2
- 2.5
- 2.5
- ns 10
Hold Times
Address status hold
t
ADSH
0.5
- 0.5
- 0.5
- ns 10
Address advance hold
t
ADVH
0.5
- 0.5
- 0.5
- ns 10
Write hold
t
WH
0.5
- 0.5
- 0.5
- ns 10
Data hold
t
DH
0.5
- 0.5
- 0.5
- ns 10
Chip enable hold
t
CEH
0.5
- 0.5
- 0.5
- ns 10
ZZ stand by
t
ZZS
-
100
-
100
-
100
ns
16
ZZ recovery
t
ZZREC
100
-
100
-
100
-
ns
16
AC TEST CONDITIONS
Input pulse levels
0V to 3.0V
Input rise and fall times
1.5ns
Input timing reference levels
1.5V
Output reference levels
1.5V
Output load
See Figures 1 and 2


OUTPUT LOADS
I/O
50 ohm
Z
0
=50 ohm
30 pF
Vt=1.5V
3 .3 V
3 1 7 o h m
5 p F
3 5 1 o h m
I/O

Fig.1 Output Load Equivalent
Fig.2 Output Load Equivalent
UTRON
UT6164C64A
Rev 1.1
64K X 64 SYNCHRONOUS PIPELINED BURST CMOS SRAM
____________________________________________________________________________________________________________
____________________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80003
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
9


NOTES:

1. All voltages referenced to Vss(GND).
2. Overshoot:
V
IH
V
CC
+ 0.6V for t t
KC
/2.
Undershoot: V
IL
Vss - 0.7V for t t
KC
/2.
3. I
CC
is given with no output current. I
CC
increases with greater output loading and faster cycle times.
4. This parameter is sampled.
5. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted.
6. Output loading is specified with C
L
=5pF as in Fig. 2.
7. At any given temperature and voltage condition. t
KQHZ
is less than t
KQLZ
and t
OEHZ
is less than t
OELZ
.
8. A READ cycle is defined by byte write enables all HIGH or ADSP# LOW along with chip enables being active for the
required setup and hold times. A WRITE cycle is defined by at one byte or all byte WRITE per READ/WRITE TRUTH
TABLE.
9. OE# is a "don't care" when a byte write enable is sampled LOW.
10. This is a synchronous device. All synchronous inputs must meet specified setup and hold time, except for "don't
care" as defined in the truth table.
11. AC I/O curves are available upon request.
12. "Device Deselected" means the device is in POWER-DOWN mode as defined in the truth table. "Device Selected"
means the device is active.
13. Typical values are measured at 3.3V, 25 and 20ns cycle time.
14. Capacitance derating applies to capacitance different from the load capacitance shown in Fig. 1.
15. Capacitance derating applies to capacitance different from the load capacitance shown in Fig. 1.
16. The assertion off ZZ allows the SRAM to enter a low power state than when deselected within the time specified.






















UTRON
UT6164C64A
Rev 1.1
64K X 64 SYNCHRONOUS PIPELINED BURST CMOS SRAM
____________________________________________________________________________________________________________
____________________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80003
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
10

TIMING WAVEFORMS

READ CYCLE
tAS
tAH
tWS tWH
tWS tWH
tCES
tCEH
A1
A2
A3
Supend Burst
ADSC# initiated read
ADSP# is blacked by CE# inactive
tKC
tKH tKL
Brust Read
Single Read
Pipelined Read
CLK
ADSP#
ADSC#
ADV#
Address
GW#
BWE#
BW#[8:1]
High - Z
High - Z
tOEQ
tOEHZ
tOELZ
tOEQX
tKQX
tKQX
tKQLZ
tKQHZ
tKQ
Q1
Q2
Q2 +1
Q2 + 2
Q3
OE#
Data-Out
Data-In
Q2 +3
tADSH
tAAS
tAAH
tADSS
tADSS
tADSH
CE1#
High - Z
tCEH
tCES
CE2 and CE3# only sampled with ADSP# or ADSC#
tCEH
tCES
Unselected with CE2
CE2
CE3#
CE1# masks ADSP#






UTRON
UT6164C64A
Rev 1.1
64K X 64 SYNCHRONOUS PIPELINED BURST CMOS SRAM
____________________________________________________________________________________________________________
____________________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80003
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
11


WRITE CYCLE
tAAS
tADSS tADSH
tAAH
tAS
tAH
tWS tWH
tWS tWH
tCES tCEH
tCES tCEH
A1
A2
A3
CE# masks ADSP#
ADSC# initiated write
ADSP# is blacked by CE# inactive
tKC
tKH tKL
tADSS
tADSH
Brust Write
Single Write
CLK
ADSP#
ADSC#
ADV#
Address
GW#
BWE#
BW#[8:1]
CE1#
ADV must be inactive for ADSP# Write
GWE# allows processor addresses (and BE#=BW#)
to be pipelined during a writeback
tWS
tWH
WR1
WR2
WR3
Write
High - Z
Data-Out
Data-In
High - Z
D1
D2
D2 + 1
2c
2d
tDS
tDH
BW#[8:1] only are applied to first cycle of WR2
D2 + 2
D2 + 3
D3
OE#
Unselected
CE2 and CE3# only sampled with ADSP# or ADSC#
Unselected with CE3#
CE2
CE3#
tCEH
tCES
CE2
CE3#





UTRON
UT6164C64A
Rev 1.1
64K X 64 SYNCHRONOUS PIPELINED BURST CMOS SRAM
____________________________________________________________________________________________________________
____________________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80003
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
12


READ / WRITE CYCLE
tAAS
tADSH
tAAH
tAS
tAH
tWS tWH
tWS tWH
tCES
tCEH
tCES
tCEH
A1
A1
A3
CE# masks ADSP#
ADSC# initiated read
ADSP# is blacked by CE# inactive
tKC
tKH tKL
tADSS
tADSH
Brust Read
Single Read
CLK
ADSP#
ADSC#
ADV#
Address
GW#
BWE#
BW#[8:1]
CE1#
tADSS
Single Write
WR1
tOEQ
tOEHZ
High - Z
High - Z
tOELZ
tOEQX
tKQX
tKQLZ
tKQ
Q1
Q2
Q3
OE#
Data-Out
Data-In
Always one clock idle when switching bus direction
Q3+1
Q3+2
Q3+3
Q2
CE2
CE3#
tCEH
tCES
CE2
CE3#
CE2 and CE3# only sampled with ADSP# or ADSC#
Unselected with CE3#
Q3







UTRON
UT6164C64A
Rev 1.1
64K X 64 SYNCHRONOUS PIPELINED BURST CMOS SRAM
____________________________________________________________________________________________________________
____________________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80003
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
13
ZZ TIMING
tAAS
tAAH
tAS
tAH
tWS tWH
tWS
tWH
tCES
tCEH
tCES
tCEH
RD1
tKC
tKH tKL
tADSS
tADSH
Read
Single Read
CLK
ADSP#
ADSC#
ADV#
A[14:0]
GW#
BWE#
BW[4:1] #
CE1#
Snooze : With Data Retention
tOEQ
tOEHZ
High - Z
High - Z
tOELZ
tOEQX
tKQX
tKQLZ
tKQHZ
tKQ
1a
OE#
Data-Out
Data-In
CE2
CE3#
tCEH
tCES
CE2
CE3#
RD2
RD
RD
RD
tWH
tWS
ZZ
tZZS
tZZREC




UTRON
UT6164C64A
Rev 1.1
64K X 64 SYNCHRONOUS PIPELINED BURST CMOS SRAM
____________________________________________________________________________________________________________
____________________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80003
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
14
PACKAGE OUTLINE DIMENSION
128 QFP Package Outline Dimension

NOTE:
1.CONTROLLING DIMENSION ARE IN MILLMETERS(mm).
2.DIMENSION D1& D2 DOES NOT INCLUDE MOLD PROTRUSION.
3.COPLANARITY OF ALL LEADS SHALL BE 2.7 MILS MAX.
(BEFORE TEST) FROM THE SEATING PLANE.
UNLESS OTHERWISE SPECIFIED.
4.GENERAL PHYSICAL OUTLIN



UTRON
UT6164C64A
Rev 1.1
64K X 64 SYNCHRONOUS PIPELINED BURST CMOS SRAM
____________________________________________________________________________________________________________
____________________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80003
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
15
ORDERING INFORMAITON

PART NO.
ACCESS TIMES (ns)
PACKAGE
UT6164C64AQ-5
5
128 PIN PQFP
UT6164C64AT-5
5
128 PIN TQFP
UT6164C64AQ-6
6
128 PIN PQFP
UT6164C64AT-6
6
128 PIN TQFP