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Электронный компонент: UT61L256CJC-10E

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UTRON
UT61L256C
Rev. 1.1
32K X 8 BIT HIGH SPEED CMOS SRAM

_____________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80058
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
REVISION HISTORY
REVISION DESCRIPTION
DATE
Preliminary Rev. 0.1 Original
May 4,2001
Rev. 1.0
Sample ready and release
Jul 13,2001
Rev. 1.1
1. Add package 28-pin 300 mil skinny PDIP & Package
outline dimension
2. Add Extended temperature : -25
~85
3. Revised Low operating power consumption :
60mA
(typical)
60/50/40 mA (typical)
4. Add Standby current : 10 mA (typical)
Jan 17,2003
UTRON
UT61L256C
Rev. 1.1
32K X 8 BIT HIGH SPEED CMOS SRAM
_________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80058
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
FEATURES
Fast access time : 10/12/15 ns (max.)
Low operating power consumption :
60/50/40 mA (typical)
Standby current : 10 mA (typical)
Single 3.3V power supply
All inputs and outputs TTL compatible
Operating temperature :
Commercial : 0
~70
Extended : -25
~85
Fully static operation
Three state outputs
Package : 28-pin 300 mil SOJ
28-pin 8mm13.4mm STSOP
28-pin 300 mil skinny PDIP


GENERAL DESCRIPTION
The UT61L256C is a 262,144-bit high-speed
CMOS static random access memory organized
as 32,768 words by 8 bits. It is fabricated using
high performance, high reliability CMOS
technology.

The UT61L256C is designed for high-speed
system applications. It is particularly suited for
use in high-speed system applications.

The UT61L256C operates from a single 3.3V
power supply and all inputs and outputs are fully
TTL compatible.


FUNCTIONAL BLOCK DIAGRAM

DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
32K
8
MEMORY
ARRAY
COLUMN I/O
A0-A14
Vcc
Vss
I/O1-I/O8
CE
OE
WE
UTRON
UT61L256C
Rev. 1.1
32K X 8 BIT HIGH SPEED CMOS SRAM
_________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80058
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
PIN CONFIGURATION
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
Vcc
A8
A9
A11
A10
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
UT61L256C
SOJ
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
CE
WE
OE
A13
A14
I/O4
A11
A9
A8
A13
I/O3
A10
A14
A12
A7
A6
A5
Vcc
I/O8
I/O7
I/O6
I/O5
Vss
I/O2
I/O1
A0
A1
A2
A4
A3
UT61L256C
STSOP
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
WE
OE
CE
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
Vcc
A8
A9
A11
A10
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
UT61L256C
skinny PDIP
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
CE
WE
OE
A13
A14

PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A14
Address Inputs
I/O1 - I/O8
Data Inputs/Outputs
CE
Chip Enable Input
WE
Write Enable Input
OE
Output Enable Input
V
CC
Power
Supply
V
SS
Ground
UTRON
UT61L256C
Rev. 1.1
32K X 8 BIT HIGH SPEED CMOS SRAM
_____________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80058
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
SYMBOL
RATING
UNIT
Terminal Voltage with Respect to Vss
V
TERM
-0.5 to +4.5
V
Commercial T
A
0 to +70
Operating Temperature
Extended T
A
-25 to +85
Storage Temperature
T
STG
-65 to +150
Power Dissipation
P
D
1
W
DC Output Current
I
OUT
50
mA
Soldering Temperature (under 10 sec)
Tsolder
260
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions
for extended period may affect device reliability.
TRUTH TABLE
MODE
CE
OE
WE
I/O OPERATION
SUPPLY CURRENT
Standby
H
X
X
High - Z
I
SB
,
I
SB1
Output Disable
L
H
H
High - Z
I
CC
Read
L
L
H
D
OUT
I
CC
Write
L
X
L
D
IN
I
CC
Note: H = V
IH
, L=V
IL
, X = Don't care.

DC ELECTRICAL CHARACTERISTICS
(T
A
= 0
to 70
(C) / -25
to 85
(E) )
PARAMETER
SYMBOL TEST CONDITION
MIN. TYP. MAX. UNIT
Power Voltage
V
CC
3.0 3.3 3.6 V
Input High Voltage
V
IH
2
-
-
V
Input Low Voltage
V
IL
-
-
0.8
V
Input Leakage Current
I
LI
V
SS
V
IN
V
CC
- 1
-
1
A
Output Leakage Current
I
LO
V
SS
V
I/O
V
CC
CE = V
IH
or OE = V
IH
or
WE
= V
IL
- 1
-
1
A
Output High Voltage
V
OH
I
OH
= - 4mA
2.0
-
-
V
Output Low Voltage
V
OL
I
OL
= 8mA
-
-
0.4
V
- 10
-
60
75
mA
- 12
-
50
60
mA
Operating Power
Supply Current
I
CC
CE = V
IL ,
I
I/O
=
0mA
Cycle=Min.
- 15
-
40
50
mA
I
SB
CE
= V
IH
- 10 15 mA
Standby Power
Supply Current
I
SB1
CE
V
CC
-0.2V
- - 3 mA
Notes:
1. Overshoot : Vcc+3.0v for pulse width less than 8ns.
2. Undershoot : Vss-3.0v for pulse width less than 8ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON
UT61L256C
Rev. 1.1
32K X 8 BIT HIGH SPEED CMOS SRAM
_____________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80058
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
CAPACITANCE (T
A
=25
, f=1.0MHz)

PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Input Capacitance
C
IN
-
8 pF
Input/Output Capacitance
C
I/O
-
10 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS

Input Pulse Levels
0V to 3.0V
Input Rise and Fall Times
3ns
Input and Output Timing Reference Levels
1.5V
Output Load
C
L
=30pF, I
OH
/I
OL
=-4mA/8mA
AC ELECTRICAL CHARACTERISTICS
(T
A
= 0
to 70
(C) / -25
to 85
(E) )
(1) READ CYCLE
PARAMETER
SYMBOL UT61L256C-10 UT61L256C-12 UT61L256C-15
MIN. MAX. MIN. MAX. MIN. MAX.
UNIT
Read Cycle Time
t
RC
10 - 12 - 15 - ns
Address Access Time
t
AA
- 10 - 12 - 15
ns
Chip Enable Access Time
t
ACE
- 10 - 12 - 15
ns
Output Enable Access Time
t
OE
- 5 - 6 - 7
ns
Chip Enable to Output in Low Z
t
CLZ*
2 - 3 - 4 -
ns
Output Enable to Output in Low Z
t
OLZ*
0 - 0 - 0 -
ns
Chip Disable to Output in High Z
t
CHZ*
- 5 - 6 - 7
ns
Output Disable to Output in High Z
t
OHZ*
- 5 - 6 - 7
ns
Output Hold from Address Change
t
OH
1 - 3 - 3 -
ns
(2) WRITE CYCLE
PARAMETER
SYMBOL UT61L256C-10 UT61L256C-12 UT61L256C-15
MIN. MAX. MIN. MAX. MIN. MAX.
UNIT
Write Cycle Time
t
WC
10 - 12 - 15 - ns
Address Valid to End of Write
t
AW
8 - 10 - 12 - ns
Chip Enable to End of Write
t
CW
8 - 10 - 12 - ns
Address Set-up Time
t
AS
0 - 0 - 0 -
ns
Write Pulse Width
t
WP
8 - 9 - 10 -
ns
Write Recovery Time
t
WR
0 - 0 - 0 -
ns
Data to Write Time Overlap
t
DW
6 - 7 - 8 -
ns
Data Hold from End of Write Time
t
DH
0 - 0 - 0 -
ns
Output Active from End of Write
t
OW*
2 - 3 - 4 -
ns
Write to Output in High Z
t
WHZ*
- 1 - 7 - 8
ns
*These parameters are guaranteed by device characterization, but not production tested.