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Электронный компонент: UT61L5128-10

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UTRON
UT61L5128
Rev. 1.2
512K X 8 BIT HIGH SPEED CMOS SRAM

UTRON
TECHNOLOGY
INC. P80061
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
REVISION HISTORY
REVISION DESCRIPTION
Draft
Date
Preliminary Rev. 0.1 Original.
Jun 5, 2001
Preliminary Rev.1.0 1.Add test condition for I
SB.
2.Add note to Vcc for access time=10ns.
Jun 23,2001
Preliminary Rev.1.1 1.Revised access time : 10/12/15 ns
8ns (max.) for Vcc=3.15V~3.6V
10ns (max.) for Vcc=3.0V~3.6V
2.Add CMOS low power operating :
Operating current : 260/220mA (Icc max.)
Standby current : 10/2mA(max.)
3.Add Data retention characteristics
4.Revised Terminal Voltage with Respect to Vss(V
TERM
) :
-0.5 to V
CC
+0.5 -0.5 to 4.6
5.Revised Input high voltage (V
IH
):
2.2(min)/Vcc+0.5(max) 2.0(min)/Vcc+0.3(max)
Sep 06,2002
Rev.1.2
1. Revised Standby current : 10/2mA(max) 0.5mA(typ.)
2. Delete I
CC1
, I
CC2
3. Revised I
SB
: 30mA 3mA, I
SB1
:10mA 2mA,
4. Add I
SB
& I
SB1
(typ.) : 1mA & 2mA
5. Add Overshoot : V
IH
+6.0V for t
tRC /2.
Undershoot : V
IL
-2.0V for t
tRC /2.
6. Revised Data retention I
DR
(max) : 3mA 1mA
7. Add order information for lead free product
May 20,2003
UTRON
UT61L5128
Rev. 1.2
512K X 8 BIT HIGH SPEED CMOS SRAM

UTRON
TECHNOLOGY
INC. P80061
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
FEATURES
Fast access time :
8ns (max.) for Vcc=3.15V~3.6V
10/12ns (max.) for Vcc=3.0V~3.6V
CMOS Low operating power
Operating current :
260/240/220 mA (Icc max.)
Standby current : 0.5 mA (typ.)
Single 3.0V~3.6V power supply
Operating temperature :
Commercial : 0
~70
All TTL compatible inputs and outputs
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Data byte control :
LB
(I/O1~I/O8)
UB (I/O9~I/O16)
Package : 44-pin 400mil TSOP-II
FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
512K X 8
MEMORY
ARRAY
COLUMN I/O
A0-A18
Vcc
Vss
I/O1-I/O8
CE
OE
WE

PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A18
Address Inputs
I/O1 - I/O8
Data Inputs/Outputs
CE
Chip enable Inputs
WE
Write Enable Input
OE
Output Enable Input
V
CC
Power
Supply
V
SS
Ground
NC No
Connection
GENERAL DESCRIPTION

The UT61L5128 is a 4,194,304-bit high-speed
CMOS static random access memory organized
as 524,288 words by 8 bits. It is fabricated using
high performance, high reliability CMOS
technology.

The UT61L5128 is designed for high-speed
system applications. It is particularly suited for use
in high-density high-speed system applications.

The UT61L5128 operates from a single 3.0V~3.6V
power supply and all inputs and outputs are fully
TTL compatible.


PIN CONFIGURATION
A1
A2
A3
A4
I/O1
I/O2
I/O3
I/O4
Vcc
Vss
A17
A16
Vss
Vcc
TSOP-II
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
A15
A0
A5
A6
A7
A8
A9
A14
A13
A12
A10
NC
34
29
30
31
32
33
44
39
40
41
42
43
35
36
37
38
A11
I/O5
I/O6
I/O8
I/O7
NC
NC
NC
NC
NC
A18
NC
NC
NC
NC
CE
OE
WE
UT61L5128
UTRON
UT61L5128
Rev. 1.2
512K X 8 BIT HIGH SPEED CMOS SRAM

UTRON
TECHNOLOGY
INC. P80061
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
SYMBOL
RATING
UNIT
Terminal Voltage with Respect to Vss
V
TERM
-0.5 to 4.6
V
Operating Temperature
T
A
0 to 70
Storage Temperature
T
STG
-65 to 150
Power Dissipation
P
D
1
W
DC Output Current
I
OUT
50
mA
Soldering Temperature (under 10 sec)
Tsolder
260
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect
device reliability.
TRUTH TABLE
MODE
CE
OE
WE
I/O OPERATION
SUPPLY CURRENT
Standby
H
X
X
High - Z
I
SB
,I
SB1
Output Disable
L
H
H
High - Z
I
CC
Read
L
L
H
D
OUT
I
CC
Write
L
X
L
D
IN
I
CC
Note: H = V
IH
, L=V
IL
, X = Don't care.

DC ELECTRICAL CHARACTERISTICS
(T
A
= 0
to 70
)
PARAMETER
SYMBOL TEST CONDITION
MIN. TYP.
MAX.
UNIT
Power Voltage
Vcc
3.0 3.3
3.6
V
Input High Voltage
V
IH
*1
2.0 - V
CC
+0.3 V
Input Low Voltage
V
IL
*2
-0.3 - 0.8 V
Input Leakage Current
I
LI
V
SS
V
IN
V
CC
- 1
-
1
A
Output Leakage Current
I
LO
V
SS
V
I/O
V
CC;
Output Disabled
- 1
-
1
A
Output High Voltage
V
OH
I
OH
= -4mA
2.4
-
-
V
Output Low Voltage
V
OL
I
OL
= 8mA
-
-
0.4
V
-8
- 260 mA
-10
- 240 mA
Operating Power
Supply Current
I
CC
Cycle time=min, 100%duty,
I/O=0mA, CE =V
IL
-12
- 220 mA
Standby Current (TTL)
I
SB
CE =V
IH,
other pins =V
IL
or V
IH
-
1
3 mA
Standby Current (CMOS) I
SB1
CE =V
CC
-0.2V, other pins at 0.2V or
Vcc-0.2V
- 0.5 2 mA
Notes:
1. Overshoot : Vcc+3.0v for pulse width less than 6ns.
2. Undershoot : Vss-3.0v for pulse width less than 6ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON
UT61L5128
Rev. 1.2
512K X 8 BIT HIGH SPEED CMOS SRAM

UTRON
TECHNOLOGY
INC. P80061
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
CAPACITANCE
(T
A
=25
, f=1.0MHz)
PARAMETER
SYMBOL MIN.
MAX.
UNIT
Input Capacitance
C
IN
-
8
pF
Input/Output Capacitance
C
I/O
-
10
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0V to 3.0V
Input Rise and Fall Times
3ns
Input and Output Timing Reference Levels
1.5V
Output Load
C
L
=30pF, I
OH
/I
OL
=-4mA/8mA

AC ELECTRICAL CHARACTERISTICS
(T
A
= 0
to 70
)
(1) READ CYCLE
UT61L5128-8
3.15V~3.6V
UT61L5128-10
3.0V~3.6V
UT61L5128-12
3.0V~3.6V
PARAMETER
SYMBOL
MIN. MAX. MIN. MAX. MIN. MAX.
UNIT
Read Cycle Time
t
RC
8 - 10 - 12 -
ns
Address Access Time
t
AA
- 8 - 10 - 12
ns
Chip Enable Access Time
t
ACE
- 8 - 8 - 8 ns
Output Enable Access Time
t
OE
- 4 - 5 - 6 ns
Chip Enable to Output in Low Z
t
CLZ*
3 - 3 - 3 - ns
Output Enable to Output in Low Z
t
OLZ*
0 - 0 - 0 - ns
Chip Disable to Output in High Z
t
CHZ*
- 4 - 5 - 6 ns
Output Disable to Output in High Z
t
OHZ*
- 4 - 5 - 6 ns
Output Hold from Address Change
t
OH
3 - 3 - 3 - ns
(2) WRITE CYCLE
UT61L5128-8
3.15V~3.6V
UT61L5128-10
3.0V~3.6V
UT61L5128-12
3.0V~3.6V
PARAMETER
SYMBOL
MIN. MAX. MIN. MAX. MIN. MAX.
UNIT
Write Cycle Time
t
WC
8 - 10 - 12 -
ns
Address Valid to End of Write
t
AW
7 - 8 - 9 - ns
Chip Enable to End of Write
t
CW
7 - 8 - 9 - ns
Address Set-up Time
t
AS
0 - 0 - 0 - ns
Write Pulse Width
t
WP
7 - 8 - 9 - ns
Write Recovery Time
t
WR
0 - 0 - 0 - ns
Data to Write Time Overlap
t
DW
5.5 - 6 - 7 - ns
Data Hold from End of Write Time
t
DH
0 - 0 - 0 - ns
Output Active from End of Write
t
OW*
3 - 3 - 0 - ns
Write to Output in High Z
t
WHZ*
- 4 - 5 - 6 ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON
UT61L5128
Rev. 1.2
512K X 8 BIT HIGH SPEED CMOS SRAM

UTRON
TECHNOLOGY
INC. P80061
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
(1,2,4)
t
O
H
t
RC
t
AA
t
O
H
Data Valid
Address
Dout

READ CYCLE 2 ( CE , and OE Controlled) (1,3,5,6)

Notes :
1.
WE
is HIGH for a read cycle.
2. Device is continuously selected CE =V
IL .
3. Address must be valid prior to or coincident with CE
transition; otherwise t
AA
is the limiting parameter.
4.
OE
is low.
5. t
CLZ,
t
OLZ
, t
CHZ
and t
OHZ
are specified with C
L
=5pF. Transition is measured
500mV from steady state.
6. At any given temperature and voltage condition, t
CHZ
is less than t
CLZ
, t
OHZ
is less than t
OLZ.

t
RC
t
AA
t
ACE
t
OE
t
CHZ
t
OHZ
t
CLZ
t
OH
t
OLZ
HIGH-Z
Data Valid
HIGH-Z
Address
CE
OE
Dout