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Электронный компонент: UT61L512LC-10

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UTRON
UT61L512
Rev 1.2
64K X 8 BIT HIGH SPEED CMOS SRAM

UTRON TECHNOLOGY INC.
P80024
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
FEATURES
Fast access time : 10/12/15 ns (max.)
Low operating power consumption :
60 mA (typical)
Single 3.3V power supply
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Package : 32-pin 300 mil SOJ
32-pin 8mmx20mm TSOP-I

FUNCTIONAL BLOCK DIAGRAM
MEMORY ARRAY
512 ROWS X 1024 COLUMNS
COLUMN I/O
COLUMN DECODER
I/O
CONTROL
LOGIC
CONTROL
I/O1
VSS
VCC
WE
OE
CE1
I/O8
.
.
.
.
.
.
. .
.
A11 A9 A3 A2
A0
.
.
.
.
.
.
2
CE
A10
A1
ROW
DECODER
A15
A13
A14
A12
A7
A6
A5
A4
A8
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A15
Address Inputs
I/O1 - I/O8
Data Inputs/Outputs
CE1,CE2
Chip Enable 1, 2 Inputs
WE
Write Enable Input
OE
Output Enable Input
V
CC
Power
Supply
V
SS
Ground
NC No
Connection




GENERAL DESCRIPTION

The UT61L512 is a 524,288-bit high-speed
CMOS static random access memory organized
as 524,288 words by 8 bits. It is fabricated using
high performance, high reliability CMOS
technology.

The UT61L512 is designed for high-speed
system applications. It is particularly suited for
use in high-density high-speed system
applications.

The UT61L512 operates from a single 3.3V
power supply and all inputs and outputs are fully
TTL compatible.
PIN CONFIGURATION
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
CE2
A8
A9
A11
A10
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
UT61L512
SOJ
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
1
CE
WE
OE
A13
A14
NC
NC
Vcc
A15
29
30
31
32
A11
A9
A8
A13
I/O3
A10
A14
A12
A7
A6
A5
Vcc
I/O8
I/O7
I/O6
I/O5
Vss
I/O2
I/O1
A0
A1
A2
A4
A3
UT61L512
TSOP-1
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
WE
OE
1
CE
CE2
NC
A15
32
31
30
29
NC
I/O4
UTRON
UT61L512
Rev 1.2
32K X 8 BIT HIGH SPEED CMOS SRAM

UTRON TECHNOLOGY INC.
P80024
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
SYMBOL
RATING
UNIT
Terminal Voltage with Respect to Vss
V
TERM
-0.5 to +7.0
V
Operating Temperature
T
A
0 to +70
Storage Temperature
T
STG
-65 to +150
Power Dissipation
P
D
1
W
DC Output Current
I
OUT
50
mA
Soldering Temperature (under 10 sec)
Tsolder
260
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may
affect device reliability.
TRUTH TABLE
MODE
1
CE
CE2
OE
WE
I/O OPERATION
SUPPLY CURRENT
Standby
H
X
X
X
High - Z
I
SB
,
I
SB1
Standby
X
L
X
X
High -Z
I
SB
,
I
SB1
Output Disable
L
H
H
H
High - Z
I
CC
Read
L
H
L
H
D
OUT
I
CC
Write
L
H
X
L
D
IN
I
CC
Note: H = V
IH
, L=V
IL
, X = Don't care.

DC ELECTRICAL CHARACTERISTICS
(V
CC
=3.1V~3.6V, T
A
= 0
to 70
)
PARAMETER
SYMBOL TEST CONDITION
MIN. MAX.
UNIT
Input High Voltage
V
IH
2.2
V
CC
+0.5 V
Input Low Voltage
V
IL
- 0.5 0.8
V
Input Leakage Current
I
LI
V
SS
V
IN
V
CC
- 1 1
A
Output Leakage Current
I
LO
V
SS
V
I/O
V
CC
CE1 = V
IH
or
CE2 =
V
IL
or OE = V
IH
or
WE
= V
IL
- 1
1
A
Output High Voltage
V
OH
I
OH
= - 4mA
2.4
-
V
Output Low Voltage
V
OL
I
OL
= 8mA
-
0.4
V
Operating Power
I
CC
CE1 = V
IL ,
CE2 =
V
IH
- 10
-
180
mA
Supply Current
I
I/O
=
0mA , Cycle=Min.
- 12
-
160
mA
- 15
-
140
mA
Standby Power
I
SB
CE1 = V
IH or
CE2 =
V
IL
-
30
mA
Supply Current
I
SB1
CE1
V
CC
-0.2V or CE2
0.2V
-
5
mA
Notes:
1. Overshoot : Vcc+3.0v for pulse width less than 8ns.
2. Undershoot : Vss-3.0v for pulse width less than 8ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON
UT61L512
Rev 1.2
32K X 8 BIT HIGH SPEED CMOS SRAM

UTRON TECHNOLOGY INC.
P80024
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
CAPACITANCE (T
A
=25
, f=1.0MHz)

PARAMETER
SYMBOL MIN.
MAX.
UNIT
Input Capacitance
C
IN
-
8
pF
Input/Output Capacitance
C
I/O
-
10
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS

Input Pulse Levels
0V to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Reference Levels
1.3.3V
Output Load
C
L
=30pF, I
OH
/I
OL
=-4mA/8mA
AC ELECTRICAL CHARACTERISTICS (V
CC
= 3.1V~3.6V , T
A
= 0
to 70
)
(1) READ CYCLE
PARAMETER
SYMBOL
UT61L512-10
UT61L512-12 UT61L512-15 UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time
t
RC
10 -
12 -
15 -
ns
Address Access Time
t
AA
-
10 -
12 -
15 ns
Chip Enable Access Time
t
ACE1,
t
ACE1
-
10 -
12 -
15 ns
Output Enable Access Time
t
OE
-
5 -
6 -
7 ns
Chip Enable to Output in Low Z
t
CLZ1*,
t
CLZ2*
2 -
3 -
4 -
ns
Output Enable to Output in Low Z
t
OLZ*
0 -
0 -
0 -
ns
Chip Disable to Output in High Z
t
CHZ1*,
t
CHZ2*
-
5 -
6 -
7
ns
Output Disable to Output in High Z
t
OHZ*
-
5 -
6 -
7
ns
Output Hold from Address Change
t
OH
3 -
3 -
3 -
ns
(2) WRITE CYCLE
PARAMETER
SYMBOL UT61L512-10 UT61L512-12 UT61L512-15 UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Write Cycle Time
t
WC
10 -
12 -
15 -
ns
Address Valid to End of Write
t
AW
8
-
10 -
12 -
ns
Chip Enable to End of Write
t
CW1,
t
CW2
8
-
10 -
12 -
ns
Address Set-up Time
t
AS
0
-
0 -
0
-
ns
Write Pulse Width
t
WP
8
-
9 -
10 -
ns
Write Recovery Time
t
WR
0
-
0 -
0
-
ns
Data to Write Time Overlap
t
DW
6
-
7 -
8
-
ns
Data Hold from End of Write Time
t
DH
0
-
0 -
0
-
ns
Output Active from End of Write
t
OW*
2
-
3 -
4
-
ns
Write to Output in High Z
t
WHZ*
-
6
-
7 -
8 ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON
UT61L512
Rev 1.2
32K X 8 BIT HIGH SPEED CMOS SRAM

UTRON TECHNOLOGY INC.
P80024
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
(1,2,4)
t
RC
Address
DOUT
Data Valid
t
AA
t
OH
t
OH

READ CYCLE 2
(
CE1
, CE2 and
OE
Controlled)
(1,3,5,6)






















Notes :
1.
WE
is HIGH for read cycle.
2. Device is continuously selected CE1=V
IL
and CE2=V
IH.
3. Address must be valid prior to or coincident with CE1and CE2 transition; otherwise t
AA
is the limiting parameter.
4. OE is low.
5. t
CLZ1
, t
CLZ2
, t
OLZ
, t
CHZ1
, t
CHZ2
and t
OHZ
are specified with C
L
=5pF. Transition is measured
500mV from steady state.
6. At any given temperature and voltage condition, t
CHZ1
is less than t
CLZ1
, t
CHZ2
is less than t
CLZ2
, t
OHZ
is less than t
OLZ.
t
RC
t
AA
t
ACE1
t
ACE2
t
OE
t
OLZ
t
CLZ1
t
CLZ2
High-Z
t
CHZ1
t
CHZ2
t
OHZ
t
OH
Data Valid
High-Z
Address
1
CE
CE2
OE
D
OUT
UTRON
UT61L512
Rev 1.2
32K X 8 BIT HIGH SPEED CMOS SRAM

UTRON TECHNOLOGY INC.
P80024
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
WRITE CYCLE 1
(
WE
Controlled)
(1,2,3,5)
Address
D
OUT
High-Z
1
CE
WE
Data Valid
D
IN
CE2
t
CW2
t
CW1
t
AW
t
WC
t
WHZ
t
WP
t
AS
t
OW
t
DW
t
DH
t
WR
(4)
(4)

WRITE CYCLE 2
(
CE1
and CE2 Controlled)
(1,2,5)
Address
D
OUT
High-Z
1
CE
WE
(4)
Data Valid
D
IN
CE2
t
WC
t
AS
t
CW1
t
AW
t
CW2
t
WR
t
WP
t
WHZ
t
DW
t
DH
Notes :
1.
WE
or CE1 must be HIGH during all address transitions.
2. A write occurs during the overlap of a low CE1 and a low
WE
.
3. During a
WE
controlled with write cycle with OE LOW, t
WP
must be greater than t
WHZ
+t
DW
to allow the drivers to turn off
and data to be placed on the bus.
4. During this period, I/O pins are in the output state, and input singals must not be applied.
5. If the CE1LOW transition occurs simultaneously with or after
WE
LOW transition, the outputs remain in a high impedance
state.
6. t
OW
and t
WHZ
are specified with C
L
= 5pF. Transition is measured
500mV from steady state.