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Электронный компонент: UT621024

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UTRON
UT621024
Rev. 1.6
128K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
REVISION HISTORY
REVISION DESCRIPTION
DATE
REV. 1.0
Original.
Apr.05 2000
REV. 1.1
NA
--
REV. 1.2
NA
--
REV. 1.3
Add STSOP-I Package
Aug.29.2000
REV. 1.4
Modify the format of power consumption
Sep.01.2000
REV. 1.5 1. Operating : 60/40 -> 60/50/40
2. Standby Current : 10 ->2 (L-version)
3. Add I
CC
data as (-55, TYP 50, MAX 85)
4. Revise I
SB1
TYP : 10-> 2, MAX : 300/100 ->100/40
5. The symbols CE1# ,OE# & WE# are revised as CE , OE &
WE
Jun.18,2001
REV. 1.6 Add order information for lead free product
May.15,2003
UTRON
UT621024
Rev. 1.6
128K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC.
P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2

FEATURES
Access time : 35/55/70ns (max.)
Low power consumption :
Operating : 60/50/40 mA (typical)
Standby : 2
A (typical) L-version
1
A (typical) LL-version
Single 5V power supply
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 32-pin 600 mil PDIP
32-pin 450 mil SOP
32-pin 8mmx20mm TSOP-1
32-pin 8mmx13.4mm STSOP

FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
1024 X 1024
MEMORY
ARRAY
COLUMN I/O
OE
WE
A0-A16
Vcc
Vss
I/O1-I/O8
CE
CE2

PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A16
Address Inputs
I/O1 - I/O8
Data Inputs/Outputs
CE ,CE2
Chip enable 1,2 Inputs
WE
Write Enable Input
OE
Output Enable Input
V
CC
Power
Supply
V
SS
Ground
NC No
Connection


GENERAL DESCRIPTION

The UT621024 is a 1,048,576-bit low power CMOS
static random access memory organized as
131,072 words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.
The UT621024 is designed for low power
application. It is particularly well suited for battery
back-up nonvolatile memory application.

The UT621024 operates from a single 5V power
supply and all inputs and outputs are fully TTL
compatible.

PIN CONFIGURATION
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
CE2
A8
A9
A11
A10
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
UT621024
PDIP / SOP
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
CE
WE
OE
A13
A14
NC
A16
Vcc
A15
29
30
31
32
TSOP-I/STSOP
I/O4
A11
A9
A8
A13
I/O3
A10
A14
A12
A7
A6
A5
Vcc
I/O8
I/O7
I/O6
I/O5
Vss
I/O2
I/O1
A0
A1
A2
A4
A3
UT621024
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
WE
OE
CE
CE2
NC
A15
A16
32
31
30
29
UTRON
UT621024
Rev. 1.6
128K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3

ABSOLUTE MAXIMUM RATINGS
*
PARAMETER
SYMBOL
RATING
UNIT
Terminal Voltage with Respect to Vss
V
TERM
-0.5 to +7.0
V
Operating Temperature
T
A
0 to +70
Storage Temperature
T
STG
-65 to +150
Power Dissipation
P
D
1
W
DC Output Current
I
OUT
50
mA
Soldering Temperature (under 10 sec)
T
solder
260
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
CE
CE2
OE
WE
I/O OPERATION
SUPPLY CURRENT
Standby
H
X
X
X
High - Z
I
SB
,
I
SB1
Standby
X
L
X
X
High -Z
I
SB
,
I
SB1
Output Disable
L
H
H
H
High - Z
I
CC
Read
L
H
L
H
D
OUT
I
CC
Write
L
H
X
L
D
IN
I
CC
Note: H = V
IH
, L=V
IL
, X = Don't care.
DC ELECTRICAL CHARACTERISTICS (V
CC
= 5V
10%, T
A
= 0
to 70
)
PARAMETER
SYMBOL TEST CONDITION
MIN. TYP. MAX.
UNIT
Input High Voltage
V
IH
*1
2.2 -
V
CC
+0.5 V
Input Low Voltage
V
IL
*2
- 0.5
-
0.8
V
Input Leakage Current
I
IL
V
SS
V
IN
V
CC
- 1
-
1
A
Output Leakage Current
I
OL
V
SS
V
I/O
V
CC
CE =V
IH
or CE2 = V
IL
or
OE
= V
IH
or
WE
= V
IL

- 1
-
1
A
Output High Voltage
V
OH
I
OH
= - 1mA
2.4
-
-
V
Output Low Voltage
V
OL
I
OL
= 4mA
-
-
0.4
V
I
CC
Cycle time=min, 100% duty,
CE =V
IL
, CE2 = V
IH
,
I
I/O
= 0mA
-35
-55
-70
-
-
-
60
50
40
100
85
70
mA
mA
mA
Average Operating
Power Supply Courrent
I
CC1
Cycle time=1s,100% duty,I
I/O
=0mA
.
CE
0.2V,CE2
V
CC
-0.2V,
other pins at 0.2V or V
CC
-0.2V,
- - 10
mA
I
SB
CE =V
IH
or CE2 = V
IL
other pins at 0.2V or V
CC
-0.2V,
- - 3 mA
100
- L
-
2
40*
4
A
50
Standby Power
Supply Current
I
SB1
CE
V
CC
-0.2V or
.
CE2
0.2V
other pins at 0.2V or V
CC
-0.2V, -
LL
- 1
15*
4
A
Notes:
1. Overshoot : Vcc+2.0v for pulse width less than 10ns.
2. Undershoot : Vss-2.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
4. Those parameters are for reference only under 50
UTRON
UT621024
Rev. 1.6
128K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC.
P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4

CAPACITANCE
(T
A
=25
, f=1.0MHz)

PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Input Capacitance
C
IN
-
8
pF
Input/Output Capacitance
C
I/O
-
10
pF
Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels
0V to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Reference Levels
1.5V
Output Load
C
L
=100pF, I
OH
/I
OL
=-1mA/4mA

AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5V
10% , T
A
= 0
to 70
)

(1) READ CYCLE
PARAMETER
SYMBOL
UT621024-35 UT621024-55 UT621024-70 UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time
t
RC
35 - 55 - 70 - ns
Address Access Time
t
AA
- 35 - 55 - 70 ns
Chip Enable Access Time
t
ACE
- 35 - 55 - 70 ns
Output Enable Access Time
t
OE
- 25 - 30 - 35 ns
Chip Enable to Output in Low-Z
t
CLZ
*
10 - 10 - 10 - ns
Output Enable to Output in Low-Z t
OLZ
*
5 - 5 - 5 - ns
Chip Disable to Output in High-Z
t
CHZ
*
- 25 - 30 - 35 ns
Output Disable to Output in High-Z t
OHZ
*
- 25 - 30 - 35 ns
Output Hold from Address Change t
OH
5 - 5 - 5 - ns

(2) WRITE CYCLE
PARAMETER
SYMBOL UT621024-35 UT621024-55 UT621024-70 UNIT
MIN.
MAX. MIN. MAX. MIN. MAX.
Write Cycle Time
t
WC
35
-
55
-
70
-
ns
Address Valid to End of Write
t
AW
30
-
50
-
60
-
ns
Chip Enable to End of Write
t
CW1
30
-
50
-
60
-
ns
Address Set-up Time
t
AS
0
-
0
-
0
-
ns
Write Pulse Width
t
WP
25
-
40
-
45
-
ns
Write Recovery Time
t
WR
0
-
0
-
0
-
ns
Data to Write Time Overlap
t
DW
20
-
25
-
30
-
ns
Data Hold from End of Write-Time t
DH
0
-
0
-
0
-
ns
Output Active from End of Write
t
OW
*
5
-
5
-
5
-
ns
Write to Output in High-Z
t
WHZ
*
-
15
-
20
-
25 ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON
UT621024
Rev. 1.6
128K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC.
P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5

TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
(1,2)
t
RC
t
AA
Data Valid
Address
Dout
t
OH
t
OH
Previous data valid

READ CYCLE 2
(
CE
and
CE2
and
OE
Controlled)
(1,3,4,5)
t
RC
t
AA
t
ACE
t
OE
t
OHZ
t
CLZ
t
OH
t
OLZ
High-Z
Data Valid
High-Z
t
CHZ
Address
CE2
Dout
CE
OE
Notes :
1.
WE
is high for read cycle.
2.Device is continuously selected OE =low, CE =low
,
CE2=high
.
3.Address must be valid prior to or coincident with CE =low
,
CE2=high; otherwise t
AA
is the limiting parameter.
4.t
CLZ
, t
OLZ
, t
CHZ
and t
OHZ
are specified with C
L
=5pF. Transition is measured
500mV from steady state.
5.At any given temperature and voltage condition, t
CHZ
is less than t
CLZ
, t
OHZ
is less than t
OLZ
.