UTRON
UT6264C
Rev. 1.4
8K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC.
P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
REVISION HISTORY
REVISION DESCRIPTION
Date
Preliminary Rev. 0.1 Original.
May 3 ,2001
Rev. 1.0
Revised
-
The timeing waveforms add CE2 control pin
Jun.4,2001
Rev. 1.1
Revised
-
Package outline dimension
-
Waveform.
Jan 15,2002
Rev. 1.2
Revised
-
Improve I
DR
from 20
A to 10A (LL-version , max.)
-
28-pin PDIP package outline dimension
May 14,2002
Rev. 1.3
1. Add Extended temperature : -20~85
2. Revised Operating : 45/30 mA (typ.) 40/30 mA (typ.)
3. Revised CMOS Standby : 2 0.3mA (typ.) normal
4. Revised DC characteristics :
a. Icc(-35) : 45 40mA (typ.), 60 50 mA (max)
b. Icc(-70) : 45 40mA (max.)
c. Icc1(Tcycle=1us)=
10mA(max.)
d. Icc2(Tcycle=500ns)=20mA(max.)
5. Revised "Order information" : add Extended parts
Jul 30,2002
Rev. 1.4
Add order information for lead free product
May 15,2003
UTRON
UT6264C
Rev. 1.4
8K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC.
P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
FEATURES
Access time : 35/70ns (max.)
Low power consumption :
Operating : 40/30 mA (typ.)
CMOS Standby : 0.3mA (typ.) normal
2
A (typ.) L-version
1
A (typ.) LL-version
Single 4.5V~5.5V power supply
Operating temperature :
Commercial : 0~70
Extended : -20~85
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 28-pin 600 mil PDIP
28-pin 330 mil SOP
FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
8K X 8
MEMORY
ARRAY
COLUMN I/O
OE
WE
A0-A12
Vcc
Vss
I/O1-I/O8
CE
CE2
GENERAL DESCRIPTION
The UT6264C is a 65,536-bit low power CMOS static
random access memory organized as 8,192 words by
8 bits. It is fabricated using high performance, high
reliability CMOS technology.
Easy memory expansion is provided by using two
chip enable input.( CE ,CE2) ,and supports low data
retention voltage for battery back-up operation with
low data retention current.
The UT6264C operates from a single 4.5V~5.5V
power supply and all inputs and outputs are fully TTL
compatible.
PIN CONFIGURATION
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
Vcc
A8
A9
A11
A10
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
UT6264C
PDIP/SOP
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
CE
WE
OE
CE2
NC
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A12
Address Inputs
I/O1 - I/O8
Data Inputs/Outputs
CE ,CE2
Chip Enable Inputs
WE
Write Enable Input
OE
Output Enable Input
V
CC
Power
Supply
V
SS
Ground
NC No
connection
UTRON
UT6264C
Rev. 1.4
8K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC.
P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
ABSOLUTE MAXIMUM RATINGS
*
PARAMETER
SYMBOL
RATING
UNIT
Terminal Voltage with Respect to V
SS
V
TERM
-0.5 to 7.0
V
Commercial
T
A
0 to 70
Operating Temperature
Extended
T
A
-20
to
85
Storage Temperature
T
STG
-65
to
150
Power Dissipation
P
D
1
W
DC Output Current
I
OUT
50
mA
Soldering Temperature (under 10 sec)
Tsolder
260
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
CE
CE2
OE
WE I/O OPERATION
SUPPLY CURRENT
Standby
H
X
X
X
High - Z
ISB, ISB1
Standby
X
L
X
X
High - Z
ISB, ISB1
Output Disable
L
H
H
H
High - Z
Icc,Icc1,Icc2
Read
L
H
L
H
D
OUT
Icc,Icc1,Icc2
Write
L
H
X
L
D
IN
Icc,Icc1,Icc2
note: H = V
IH
, L=V
IL
, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 4.5V~5.5V, T
A
= 0 to 70/-20 to 85(E))
PARAMETER
SYMBOL TEST CONDITION
MIN. TYP. MAX.
UNIT
Input High Voltage
V
IH
1
2.2 -
V
CC
+0.5 V
Input Low Voltage
V
IL
2
- 0.5
-
0.8
V
Input Leakage Current
I
LI
V
SS
V
IN
V
CC
- 1
-
1
A
Output Leakage Current
I
LO
V
SS
V
I/O
V
CC;
CE =V
IH;
or CE2=V
IL;
or OE = V
IH
;
or WE = V
IL
- 1
-
1
A
Output High Voltage
V
OH
I
OH
= -1mA
2.4
-
-
V
Output Low Voltage
V
OL
I
OL
= 4mA
-
-
0.4
V
- 35
-
40
50
mA
I
CC
CE = V
IL
,
I
I/O
= 0mA ,Cycle=Min.
- 70
-
30
40
mA
Icc1
Tcycle
=1s
- - 10 mA
Operating Power
Supply Current
Icc2
CE = 0.2V; I
I/O
= 0mA;
CE2=Vcc-0.2V;
other pins at 0.2V or V
CC
-0.2V Tcycle
=500ns
- -
20
mA
I
SB
CE =V
IH
or CE2= V
IL
- 1 10 mA
I
SB1
CE V
CC
-0.2V
or CE2
0.2V
normal
0.3 5 mA
I
SB
CE =V
IH
or CE2= V
IL
-L/-LL - - 3 mA
-L -
2 100 A
Standby Power
Supply Current
I
SB1
CE V
CC
-0.2V
or CE2
0.2V
-LL - 1 50 A
Notes:
1. Overshoot : Vcc+2.0v for pulse width less than 10ns.
2. Undershoot : Vss-2.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON
UT6264C
Rev. 1.4
8K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC.
P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
CAPACITANCE
(T
A
=25, f=1.0MHz)
PARAMETER
SYMBOL
MIN.
MAX
UNIT
Input Capacitance
C
IN
-
8 pF
Input/Output Capacitance
C
I/O
-
10 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0V to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Reference Levels
1.5V
Output Load
C
L
= 100pF, I
OH
/I
OL
= -1mA/4mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 4.5V~5.5V, T
A
= 0 to 70/-20 to 85(E))
(1) READ CYCLE
UT6264C-35 UT6264C-70
PARAMETER
SYMBOL
MIN. MAX. MIN. MAX.
UNIT
Read Cycle Time
t
RC
35 - 70 - ns
Address Access Time
t
AA
- 35 - 70 ns
Chip Enable Access Time
t
ACE
- 35 - 70 ns
Output Enable Access Time
t
OE
- 25 - 35 ns
Chip Enable to Output in Low-Z
t
CLZ*
10 - 10 - ns
Output Enable to Output in Low-Z
t
OLZ*
5 - 5 - ns
Chip Disable to Output in High-Z
t
CHZ*
- 25 - 35 ns
Output Disable to Output in High-Z
t
OHZ*
- 25 - 35 ns
Output Hold from Address Change
t
OH
5 - 5 - ns
(2) WRITE CYCLE
UT6264C-35 UT6264C-70
PARAMETER
SYMBOL
MIN. MAX. MIN. MAX.
UNIT
Write Cycle Time
t
WC
35 - 70 - ns
Address Valid to End of Write
t
AW
30 - 60 - ns
Chip Enable to End of Write
t
CW
30 - 60 - ns
Address Set-up Time
t
AS
0 - 0 - ns
Write Pulse Width
t
WP
25 - 50 - ns
Write Recovery Time
t
WR
0 - 0 - ns
Data to Write Time Overlap
t
DW
20 - 30 - ns
Data Hold from End of Write-Time
t
DH
0 - 0 - ns
Output Active from End of Write
t
OW*
5 - 5 - ns
Write to Output in High-Z
t
WHZ*
- 15 - 25 ns
*These parameters are guaranteed by device characterization, but not production tested.
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