UTRON
UT62L1024(I)
Rev. 1.1
128K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80078
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
REVISION HISTORY
REVISION DESCRIPTION Date
Rev. 1.0
Original.
Mar. 27. 2003
Rev. 1.1
Add order information for lead free product
May. 09. 2003
UTRON
UT62L1024(I)
Rev. 1.1
128K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80078
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
FEATURES
Fast access time : 55/70ns
CMOS low power operation
Operating current : 20/18/15mA (TYP.)
Standby current : 20 uA(TYP.) L -version
2 uA(TYP.) LL-version
Single 2.5V~3.6V power supply
Operating temperature:
Industrial : -40
~85
All TTL compatible inputs and outputs
Fully static operation
Three state outputs
Data retention voltage: 1.5V (min)
Package : 32-pin 450mil SOP
32-pin 8mm x 20mm TSOP-
32-pin 8mm x 13.4mm STSOP
36-pin 6mm 8mm TFBGA
GENERAL DESCRIPTION
The UT62L1024(I) is a 1,048,576-bit low power
CMOS static random access memory organized as
131,072 words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.
The UT62L1024(I) is designed for very low power
system applications. It is particularly well suited for
battery back-up nonvolatile memory applications.
It operates from a wide range of 2.5V~ 3.6V supply
voltage. Easy memory expansion is provided by
using two chip enable input, CE & CE2. And all
inputs and three-state outputs are fully TTL
compatible.
FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
2048 x 512
MEMORY
ARRAY
COLUMN I/O
A0-A16
Vcc
Vss
I/O1-I/O8
CE2
WE
CE
OE
UTRON
UT62L1024(I)
Rev. 1.1
128K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80078
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
PIN CONFIGURATION
A 1 2
A 7
A 6
A 5
A 4
A 3
A 2
A 1
A 0
I/O 1
I/O 2
C E 2
A 8
A 9
A 1 1
A 1 0
I/O 8
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
V s s
UT62L1024(I)
S O P
2 8
1 4
1 3
1 2
1 1
1 0
9
8
7
6
5
4
3
2
1
1 7
1 6
1 5
2 0
1 9
1 8
2 2
2 3
2 4
2 5
2 6
2 7
2 1
C E
W E
O E
A 1 3
A 1 4
N C
A 1 6
V c c
A 1 5
2 9
3 0
3 1
3 2
O E
W E
A12
A11
A13
CE2
N C
A10
A14
A15
I/O 6
I/O 7
I/O 8
A9
Vss
A8
A16
I/O 5
Vcc
Vcc
I/O 4
N C
Vss
A7
A0
I/O 3
I/O 2
I/O 1
A6
A1
A3
A5
N C
A4
A2
1
2
3
4
5
6
H
G
C
D
E
F
A
B
TFB G A
C E
TSOP-1/STSOP
I/O4
A11
A9
A8
A13
I/O3
A10
A14
A12
A7
A6
A5
Vcc
I/O7
I/O6
I/O5
Vss
I/O2
I/O1
A0
A1
A2
A4
A3
UT62L1024(I)
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
WE
OE
CE2
NC
A15
32
31
30
29
A16
CE
I/O8
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A16
Address Inputs
I/O1 - I/O8
Data Inputs/Outputs
CE ,CE2
Chip Enable Inputs
WE
Write Enable Input
OE
Output Enable Input
V
CC
Power
Supply
V
SS
Ground
NC No
Connection
UTRON
UT62L1024(I)
Rev. 1.1
128K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80078
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
TRUTH TABLE
MODE
CE
CE2
OE
WE
I/O OPERATION SUPPLY CURRENT
H
X
X
X
High - Z
I
SB
,
I
SB1
Standby
X
L
X
X
High - Z
I
SB
,
I
SB1
Output Disable
L
H
H
H
High - Z
I
CC
,
I
CC1,
I
CC2
Read
L
H
L
H
D
OUT
I
CC
,
I
CC1,
I
CC2
Write
L
H
X
L
D
IN
I
CC
,
I
CC1,
I
CC2
Note: H = V
IH
, L=V
IL
, X = Don't care.
ABSOLUTE MAXIMUM RATINGS*
PARAMETER SYMBOL
RATING
UNIT
Terminal Voltage with Respect to V
SS
V
TERM
-0.5 to 4.6
V
Operating Temperature
Industrial
T
A
-40 to 85
Storage Temperature
T
STG
-65 to 150
Power Dissipation
P
D
1
W
DC Output Current
I
OUT
50
mA
Soldering Temperature (under 10 secs)
Tsolder
260
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device
reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.5V~3.6V, T
A
= -40
to 85
)
PARAMETER
SYMBOL
TEST CONDITION
MIN. TYP. MAX. UNIT
Power Voltage
V
CC
2.5 3.0 3.6
V
Input High Voltage
V
IH
1
2.2
-
Vcc+0.3
V
Input Low Voltage
V
IL
2
-
0.2
-
0.6
V
Input Leakage Current
I
LI
V
SS
V
IN
V
CC
- 1
-
1
A
Output Leakage Current
I
LO
V
SS
V
I/O
V
CC,
Output Disabled
- 1
-
1
A
Output High Voltage
V
OH
I
OH
= - 1mA (I
OH
= -0.5mA when Vcc<2.7V)
2.2 2.7
-
V
Output Low Voltage
V
OL
I
OL
= 2.1mA
- - 0.4 V
55
- 20 35 mA
I
CC
Cycle time=Min.100% duty,
CE
=V
IL
and CE2 = V
IH
,
I
I/O
=0mA
70
- 18 30 mA
I
CC1
TCycle=
1s
-
4 5 mA
Operating Current
I
CC2
100%duty, I
I/O=
0mA,
CE
0.2V
and CE2
Vcc-0.2V, other pins
at 0.2V or Vcc-0.2V
TCycle=
500ns
-
8 10 mA
Standby Current (TTL)
I
SB
CE
=V
IH
or CE2 = V
IL
- 0.3 0.5 mA
-L
- 20 80 A
Standby Current (CMOS)
I
SB1
CE
=V
CC
-0.2V or CE2=0.2V,
other pins at 0.2V or Vcc-0.2V
-LL
- 2 10 A
Notes:
1. Overshoot : Vcc+3.0v for pulse width less than 10ns.
2. Undershoot : Vss-3.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON
UT62L1024(I)
Rev. 1.1
128K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80078
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
CAPACITANCE
(T
A
=25
, f=1.0MHz)
PARAMETER
SYMBOL
MIN.
MAX
UNIT
Input Capacitance
C
IN
-
6 pF
Input/Output Capacitance
C
I/O
-
8 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0.1V
CC
to 0.9V
CC
Input Rise and Fall Times
5ns
Input and Output Timing Reference Levels
1.5V
Output Load
C
L
= 30pF+1TTL, I
OH
= -1mA, I
OL
= 2.1mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.5V~3.6V, T
A
= - 40
to 85
)
(1) READ CYCLE
PARAMETER SYMBOL
UT62L1024(I)-55 UT62L1024(I)-70 UNIT
MIN. MAX. MIN. MAX.
Read Cycle Time
t
RC
55 - 70 - ns
Address Access Time
t
AA
- 55 - 70
ns
Chip Enable Access Time
t
ACE
- 55 - 70
ns
Output Enable Access Time
t
OE
- 30 - 35
ns
Chip Enable to Output in Low Z
t
CLZ*
10 - 10 - ns
Output Enable to Output in Low Z
t
OLZ*
5 - 5 -
ns
Chip Disable to Output in High Z
t
CHZ*
- 20 - 25
ns
Output Disable to Output in High Z
t
OHZ*
- 20 - 25
ns
Output Hold from Address Change
t
OH
10 - 10 - ns
(2) WRITE CYCLE
PARAMETER SYMBOL
UT62L1024(I)-55 UT62L1024(I)-70 UNIT
MIN. MAX. MIN. MAX.
Write Cycle Time
t
WC
55 -
70
- ns
Address Valid to End of Write
t
AW
50 -
60
- ns
Chip Enable to End of Write
t
CW
50 -
60
- ns
Address Set-up Time
t
AS
0 - 0 - ns
Write Pulse Width
t
WP
45 -
55
- ns
Write Recovery Time
t
WR
0 -
0
- ns
Data to Write Time Overlap
t
DW
25 -
30
- ns
Data Hold from End of Write Time
t
DH
0 - 0 - ns
Output Active from End of Write
t
OW*
5
-
5
- ns
Write to Output in High Z
t
WHZ*
- 20 - 25 ns
*These parameters are guaranteed by device characterization, but not production tested.
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