UTRON

UT62L256C

Rev. 1.2

32K X 8 BIT LOW POWER CMOS SRAM

___________________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80057
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919

REVISION HISTORY

REVISION DESCRIPTION Date

Preliminary Rev. 0.1 Original

May 4,2001

Rev. 1.0

Sample ready and release

Jul 16,2001

Rev. 1.1

1.Add 28-pin 8x20 mm TSOP-I
2.Add 28L 8x20mm TSOP-I outline dimension

Jul 16,2002

Rev. 1.2

Add order information for lead free product

May 13,2003

UTRON

UT62L256C

Rev. 1.2

32K X 8 BIT LOW POWER CMOS SRAM

FEATURES

Fast access time : 35/70ns (max.)

Low power consumption:

Operating current : 40/20 mA (max)

Standby current :

A (typical) L-version

0.5

A(typical) LL-version

Single 2.7V ~ 3.6V power supply

All inputs and outputs TTL compatible

Fully static operation

Three state outputs

Data retention voltage : 1.5V (min.)

Package : 28-pin 600 mil PDIP

28-pin 330 mil SOP

28-pin 8x13.4mm STSOP
28-pin 8x20 mm TSOP-I

GENERAL DESCRIPTION

The UT62L256C is a 262,144-bit low power CMOS
static random access memory organized as 32,768
words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology. Its
standby current is stable within the range of
operating temperature.

The UT62L256C is designed for high-speed and
low power application. It is particularly well suited
for battery back-up nonvolatile memory application.

The UT62L256C operates from a single
2.7V ~ 3.6V power supply and all inputs and
outputs are fully TTL compatible

FUNCTIONAL BLOCK DIAGRAM

DECODER

I/O DATA

CIRCUIT

CONTROL

CIRCUIT

32K

MEMORY

ARRAY

COLUMN I/O

A0-A14

Vcc
Vss

I/O1-I/O8

UTRON

UT62L256C

Rev. 1.2

32K X 8 BIT LOW POWER CMOS SRAM

PIN CONFIGURATION

A12

I/O1

I/O2

Vcc

A11

A10

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

Vss

UT62L256C

PDIP/SOP

A13

A14

STSOP/TSOP-I

I/O4

A11

A13

I/O3

A10

A14

A12

Vcc

I/O8

I/O7

I/O6

I/O5

Vss

I/O2

I/O1

UT62L256C

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0 - A14

Address Inputs

I/O1 - I/O8

Data Inputs/Outputs

Chip Enable Input

Write Enable Input

Output Enable Input

Power

Supply

Ground

UTRON

UT62L256C

Rev. 1.2

32K X 8 BIT LOW POWER CMOS SRAM

ABSOLUTE MAXIMUM RATINGS*

PARAMETER

SYMBOL

RATING

UNIT

Terminal Voltage with Respect to V

TERM

-0.5 to 4.5

Operating Temperature

0 to 70

Storage Temperature

STG

-65 to 150

Power Dissipation

DC Output Current

OUT

Soldering Temperature (under 10 sec)

Tsolder

260

*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

TRUTH TABLE

MODE

I/O OPERATION

SUPPLY CURRENT

Standby

High - Z

, I

SB1

Output Disable

High - Z

CC,

cc1,

cc2

Read L

OUT

CC,

cc1,

cc2

Write L

CC,

cc1,

cc2

Note: H = V

, L=V

, X = Don't care.

DC ELECTRICAL CHARACTERISTICS

= 2.7V ~ 3.6V, T

= 0

to 70

)

PARAMETER SYMBOL

TEST

CONDITION

MIN. TYP. MAX. UNIT

Input High Voltage

2.0

+0.5 V

Input Low Voltage

0.5

0.6

Input Leakage Current I

1 - 1

µA

Output Leakage

Current

I/O

CE =V

or OE = V

= V

1 - 1

µA

Output High Voltage V

= - 1mA

2.4

Output Low Voltage V

= 4mA

0.4

- 35

- 40

Cycle

time=Min.,

CE = V

I/O

= 0mA , - 70

- 20

Icc1

Cycle time=1us

CE =0.2V; I

I/O

= 0mA

other pins at 0.2V or Vcc-0.2V;

- - 6

Average Operating
Power supply Current

Icc2

Cycle time=500ns

CE =0.2V; I

I/O

= 0mA

other pins at 0.2V or Vcc-0.2V

- - 12

CE =V

- - 3

Standby Power
Supply Current

SB1

-0.2V

-L

µA

-LL

0.5

µA

Notes:
1. Overshoot : Vcc+3.0v for pulse width less than 10ns.
2. Undershoot : Vss-3.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.

UTRON

UT62L256C

Rev. 1.2

32K X 8 BIT LOW POWER CMOS SRAM

CAPACITANCE (T

=25

, f=1.0MHz)

PARAMETER

SYMBOL

MIN.

MAX

UNIT

Input Capacitance

8 pF

Input/Output Capacitance

I/O

10 pF

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels

0V to 3.0V

Input Rise and Fall Times

5ns

Input and Output Timing Reference Levels

1.5V

Output Load

= 100pF, I

= -1mA/4mA

AC ELECTRICAL CHARACTERISTICS

= 2.7V~3.6V , T

= 0

to 70

)

(1) READ CYCLE

PARAMETER

SYMBOL

UT62L256C-35 UT62L256C-70

UNIT

MIN. MAX. MIN.

MAX.

Read Cycle Time

35 - 70

Address Access Time

- 35 -

Chip Enable Access Time

ACE

- 35 -

Output Enable Access Time

- 25 -

Chip Enable to Output in Low Z

CLZ*

10 - 10

Output Enable to Output in Low Z

OLZ*

5 - 5

Chip Disable to Output in High Z

CHZ*

- 25 -

Output Disable to Output in High Z

OHZ*

- 25 -

Output Hold from Address Change

5 - 5

(2) WRITE CYCLE

PARAMETER

SYMBOL

UT62L256C-35

UT62L256C-70

UNIT

MIN. MAX. MIN.

MAX.

Write Cycle Time

35 - 70

Address Valid to End of Write

30 - 60

Chip Enable to End of Write

30 - 60

Address Set-up Time

0 - 0

Write Pulse Width

25 - 50

Write Recovery Time

0 - 0

Data to Write Time Overlap

20 - 30

Data Hold from End of Write Time

0 - 0

Output Active from End of Write

OW*

5 - 5

Write to Output in High Z

WHZ*

- 15 -

*These parameters are guaranteed by device characterization, but not production tested.

UTRON

UT62L256C

Rev. 1.2

32K X 8 BIT LOW POWER CMOS SRAM

TIMING WAVEFORMS

READ CYCLE 1

(Address Controlled)

(1,2)

Data Valid

Address

Dout

Previous data valid

READ CYCLE 2

(

and

Controlled)

(1,3,4,5)

ACE

OHZ

CLZ

OLZ

High-Z

Data Valid

High-Z

CHZ

Address

Dout

Notes :
1.

is high for read cycle.

2.Device is continuously selected OE =low, CE =low

3.Address must be valid prior to or coincident with CE =low

; otherwise t

is the limiting parameter.

4.t

CLZ

, t

OLZ

, t

CHZ

and t

OHZ

are specified with C

=5pF. Transition is measured

500mV from steady state.

5.At any given temperature and voltage condition, t

CHZ

is less than t

CLZ

, t

OHZ

is less than t

OLZ

UTRON

UT62L256C

Rev. 1.2

32K X 8 BIT LOW POWER CMOS SRAM

WRITE CYCLE 1

(

Controlled)

(1,2,3,5,6)

WHZ

High-Z

(4)

Address

Dout

Din

Data Valid

WRITE CYCLE 2

(

Controlled)

(1,2,5,6)

W C

A W

C W

A S

W R

W P

W H Z

D W

D H

Data Valid

High-Z

(4)

Address

W E

Dout

Din

UTRON

UT62L256C

Rev. 1.2

32K X 8 BIT LOW POWER CMOS SRAM

Notes :

, CE must be high during all address transitions.

2.A write occurs during the overlap of a low CE , low

3.During a

controlled write cycle with OE low, t

must be greater than t

WHZ

to allow the drivers to turn off and data to be

placed on the bus.

4.During this period, I/O pins are in the output state, and input signals must not be applied.

5.If the CE low transition occurs simultaneously with or after

low transition, the outputs remain in a high impedance state.

6.t

and t

WHZ

are specified with C

= 5pF. Transition is measured

500mV from steady state.

DATA RETENTION CHARACTERISTICS

= 0

to 70

)

PARAMETER SYMBOL

TEST

CONDITION

MIN. TYP.

MAX.

UNIT

Vcc for Data Retention

-0.2V

1.5 - 3.6

Data Retention Current

Vcc=2.5V

- L

µA

-0.2V

- LL

0.5

µA

Chip Disable to Data

CDR

See Data Retention

0 - -

Retention Time

Waveforms (below)

Recovery Time

RC*

- - ns

RC*

= Read Cycle Time

DATA RETENTION WAVEFORM

1.5V

-0.2V

cc(min.)

CDR

UTRON

UT62L256C

Rev. 1.2

32K X 8 BIT LOW POWER CMOS SRAM

PACKAGE OUTLINE DIMENSION

28 pin 600 mil PDIP PACKAGE OUTLINE DIMENSION

UNIT

SYMBOL

INCH(BASE) MM(REF)

0.010 (MIN)

0.254 (MIN)

0.150

0.005 3.810

0.127

B 0.020

(MAX)

0.508(MAX)

B1 0.055

(MAX)

1.397(MAX)

0.012 (MAX)

0.304 (MAX)

1.430 (MAX) 36.322 (MAX)

0.6 (TYP)

15.24 (TYP)

0.52 (MAX)

13.208 (MAX)

e 0.100

(TYP)

2.540(TYP)

0.625 (MAX)

15.87 (MAX)

L 0.180(MAX)

4.572(MAX)

0.06 (MAX)

1.524 (MAX)

Q1 0.08(MAX)

2.032(MAX)

(MAX) 15

(MAX)

UTRON

UT62L256C

Rev. 1.2

32K X 8 BIT LOW POWER CMOS SRAM

28 pin 330 mil SOP PACKAGE OUTLINE DIMENSION

UNIT

SYMBOL

INCH(BASE) MM(REF)

0.120 (MAX)

3.048 (MAX)

A1 0.002(MIN)

0.05(MIN)

0.098

0.005 2.489

0.127

b 0.0016

(TYP)

0.406(TYP)

c 0.010

(TYP)

0.254(TYP)

0.728 (MAX) 18.491 (MAX)

0.340 (MAX)

8.636 (MAX)

0.465

0.012 11.811

0.305

e 0.050

(TYP)

1.270(TYP)

0.05 (MAX)

1.270 (MAX)

0.067

0.008 1.702

0.203

0.047 (MAX)

1.194 (MAX)

y 0.003(MAX)

0.076(MAX)

UTRON

UT62L256C

Rev. 1.2

32K X 8 BIT LOW POWER CMOS SRAM

28 pin 8x13.4mm STSOP PACKAGE OUTLINE DIMENSION

Note

E dimension is not including end flash
The total of both sides' end flash is
Not above 0.3mm.

UNIT

SYMBOL

INCH(BASE) MM(REF)

0.047 (MAX)

1.20 (MAX)

0.004

0.002 0.10

0.05

0.039

0.002 1.00

0.05

b 0.006

(TYP)

0.15(TYP)

c 0.010

(TYP)

0.254(TYP)

0.465

0.004 11.80

0.10

0.315

0.004 8.00

0.10

e 0.022

(TYP)

0.55(TYP)

0.528

0.008 13.40

0.20

0.020

0.004 0.50

0.10

0.0315

0.004 0.80

0.10

y 0.08(MAX)

0.003(MAX)

UTRON

UT62L256C

Rev. 1.2

32K X 8 BIT LOW POWER CMOS SRAM

28 pin 8x20mm TSOP-I PACKAGE OUTLINE DIMENSION

Note

E dimension is not including end flash
The total of both sides' end flash is
Not above 0.3mm.

UNIT

SYMBOL

INCH(BASE) MM(REF)

0.047 (MAX)

1.20 (MAX)

0.004

0.002 0.10

0.05

0.039

0.002 1.00

0.05

b 0.008

(TYP)

0.20(TYP)

c 0.008

(TYP)

0.15(TYP)

0.465

0.004 11.80

0.10

0.315

0.004 8.00

0.10

e 0.022

(TYP)

0.55(TYP)

0.528

0.008 13.40

0.20

0.020

0.004 0.50

0.10

0.0315

0.004 0.80

0.10

y 0.003(MAX)

0.08(MAX)

UTRON

UT62L256C

Rev. 1.2

32K X 8 BIT LOW POWER CMOS SRAM

ORDERING INFORMATION

PART NO.

ACCESS TIME

(ns)

STANDBY CURRENT

(

A) typ.

PACKAGE

UT62L256CPC-35L 35

1 µA

28PIN PDIP

UT62L256CPC-35LL 35

0.5 µA

28PIN PDIP

UT62L256CPC-70L 70

1 µA

28PIN PDIP

UT62L256CPC-70LL 70

0.5 µA

28PIN PDIP

UT62L256CSC-35L 35

1 µA

28PIN SOP

UT62L256CSC-35LL 35

0.5 µA

28PIN SOP

UT62L256CSC-70L 70

1 µA

28PIN SOP

UT62L256CSC-70LL 70

0.5 µA

28PIN SOP

UT62L256CLS-35L 35

1 µA

28PIN STSOP

UT62L256CLS-35LL 35

0.5 µA

28PIN STSOP

UT62L256CLS-70L 70

1 µA

28PIN STSOP

UT62L256CLS-70LL 70

0.5 µA

28PIN STSOP

UT62L256CLC-35L 35

1 µA

28PIN TSOP-I

UT62L256CLC-35LL 35

0.5 µA

28PIN TSOP-I

UT62L256CLC-70L 70

1 µA

28PIN TSOP-I

UT62L256CLC-70LL 70

0.5 µA

28PIN TSOP-I

ORDERING INFORMATION (for lead free product)

PART NO.

ACCESS TIME

(ns)

STANDBY CURRENT

(

A) typ.

PACKAGE

UT62L256CPCL-35L 35

1 µA

28PIN PDIP

UT62L256CPCL-35LL 35

0.5 µA

28PIN PDIP

UT62L256CPCL-70L 70

1 µA

28PIN PDIP

UT62L256CPCL-70LL 70

0.5 µA

28PIN PDIP

UT62L256CSCL-35L 35

1 µA

28PIN SOP

UT62L256CSCL-35LL 35

0.5 µA

28PIN SOP

UT62L256CSCL-70L 70

1 µA

28PIN SOP

UT62L256CSCL-70LL 70

0.5 µA

28PIN SOP

UT62L256CLSL-35L 35

1 µA

28PIN STSOP

UT62L256CLSL-35LL 35

0.5 µA

28PIN STSOP

UT62L256CLSL-70L 70

1 µA

28PIN STSOP

UT62L256CLSL-70LL 70

0.5 µA

28PIN STSOP

UT62L256CLCL-35L 35

1 µA

28PIN TSOP-I

UT62L256CLCL-35LL 35

0.5 µA

28PIN TSOP-I

UT62L256CLCL-70L 70

1 µA

28PIN TSOP-I

UT62L256CLCL-70LL 70

0.5 µA

28PIN TSOP-I

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UT62L256CSCL-70L