UTRON
UT62L25716(I)
Rev. 1.3
256K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC.
P80046
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
REVISION HISTORY
REVISION DESCRIPTION
Draft
Date
Preliminary Rev. 0.5
Original.
Mar, 2001
Rev.1.0
1.Separate Industrial and Commercial SPEC.
2.New waveforms.
3.Add access time 55ns range.
4.The symbols CE1# and OE# and WE# are revised as.
1
CE and
OE and
WE
.
Aug 7,2001
Rev.1.1
1.Revised access time 55/70/100ns
-Rev 1.0: 55ns(max) for Vcc=3.0V~3.6V
70/100 ns(max) for Vcc=2.7V~3.6V
2.Revised "SYMBOL" :
1
CE
CE
3.Revised ABSOLUTE MAXIMUM RATINGS
- V
TERM
: -0.3 to 4.6 -0.5 to 4.6V
- P
D :
1.0~1.5 1W
- I
OUT
: 50 20mA
4.Revised DC CHARACTERISTICS
- V
IH
: 2.0 2.2V
5.Revised AC CHARACTERISTICS
- t
OH
& t
BLZ
: 5 10ns
6.Revised 48-pin TFBGA package outline dimension
-ball diameter : 0.3mm 0.35mm
Nov 8 ,2002
Rev.1.2
1. Revised Standby current (LL-Version) : 3uA(typ) 2uA(typ)
2. Revised operating current (Iccmax) : 45/35/25mA 40/30/25mA
3. Revised DC CHARACTERISTICS :
a. Operating Power Supply Current (Icc)
55ns (max) : 45 40mA
70ns (typ) : 25 20mA, 70ns (max) : 35 30mA
100ns (Typ) : 20 16mA
b. Standby current(CMOS) :
LL-version (typ) : 3 2uA, 25 20uA
Dec 3,2002
Rev.1.3
1. Revised V
OH
(Typ) : NA 2.7V
2. Add V
IH
(max)=V
CC
+2.0V for pulse width less than 10ns.
V
IL
(min)=V
SS
-2.0V for pulse width less than 10ns.
3. Add order information for lead free product
May 6,2003
UTRON
UT62L25716(I)
Rev. 1.3
256K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC.
P80046
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
FEATURES
Fast access time : 55/70/100ns
CMOS low power operating
Operating current : 40/30/25 (Icc,max.)
Standby current : 20uA (TYP.) L-version
2uA (TYP.) LL-version
Single 2.7V~3.6V power supply
Operation temperature:
Industrial : -40
~85
All TTL compatible inputs and outputs
Fully static operation
Three state outputs
Data retention voltage:1.5V (min.)
Data byte control :
LB
(I/O1~I/O8)
UB (I/O9~I/O16)
Package : 48-pin 6mm 8mm TFBGA
GENERAL DESCRIPTION
The UT62L25716(I) is a 4,194,304-bit low power
CMOS static random access memory organized as
262,144 words by 16 bits.
The UT62L25716(I) operates from a single 2.7V ~
3.6V power supply and all inputs and outputs are
fully TTL compatible.
The UT62L25716(I) is designed for low power
system applications. It is particularly well suited for
use in high-density low power system applications.
FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
256K X 16
MEMORY
ARRAY
COLUMN I/O
A0-A17
Vcc
Vss
I/O1-I/O8
Lower Byte
I/O9-I/O16
Upper Byte
CE2
OE
WE
LB
UB
CE
UTRON
UT62L25716(I)
Rev. 1.3
256K X 16 BIT LOW POWER CMOS
SRAM
UTRON TECHNOLOGY INC.
P80046
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
PIN CONFIGURATION
LB
A0
OE
A1
CE2
A2
I/O9
A3
UB
A4
I/O1
CE
I/O10
A5
I/O11
A6
I/O3
I/O2
Vss
A17
I/O12
A7
Vcc
I/O4
Vcc
NC
I/O13
A16
Vss
I/O5
I/O15
A14
I/O14
A15
I/O7
I/O6
I/O16
A12
NC
A13
I/O8
WE
NC
A9
A8
A10
NC
A11
1
2
3
4
5
6
H
G
C
D
E
F
A
B
TFBGA
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0 - A17
Address Inputs
I/O1 - I/O16 Data Inputs/Outputs
CE , CE2
Chip Enable Input
WE
Write Enable Input
OE
Output Enable Input
LB
Lower-byte Control
UB
Upper-byte Control
V
CC
Power
Supply
V
SS
Ground
NC No
Connection
TRUTH TABLE
I/O OPERATION
MODE
CE
CE2
OE
WE
LB
UB
I/O1-I/O8 I/O9-I/O16
SUPPLY
CURRENT
Standby
H
X
X
X
L
X
X
X
X
X
X
X
X
X
H
X
X
H
High Z
High Z
High Z
High Z
High Z
High Z
I
SB
, I
SB1
Output Disable
L
L
H
H
H
H
H
H
L
X
X
L
High Z
High Z
High Z
High Z
I
CC
,I
CC1
,I
CC2
Read
L
L
L
H
H
H
L
L
L
H
H
H
L
H
L
H
L
L
D
OUT
High Z
D
OUT
High Z
D
OUT
D
OUT
I
CC
,I
CC1
,I
CC2
Write
L
L
L
H
H
H
X
X
X
L
L
L
L
H
L
H
L
L
D
IN
High Z
D
IN
High Z
D
IN
D
IN
I
CC
,I
CC1
,I
CC2
Note: H = V
IH
, L=V
IL
, X = Don't care.
UTRON
UT62L25716(I)
Rev. 1.3
256K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC.
P80046
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
ABSOLUTE MAXIMUM RATINGS*
PARAMETER SYMBOL
RATING
UNIT
Terminal Voltage with Respect to V
SS
V
TERM
-0.5 to 4.6
V
Operating Temperature
Industrial
T
A
-40 to 85
Storage Temperature
T
STG
-65 to 150
Power Dissipation
P
D
1
W
DC Output Current
I
OUT
50
mA
Soldering Temperature (under 10 secs)
Tsolder
260
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(Vcc = 2.7V~3.6V, T
A
= -40
to 85
(I))
PARAMETER
SYMBOL
TEST CONDITION
MIN. TYP. MAX. UNIT
Power Voltage
V
CC
2.7 3.0 3.6 V
Input High Voltage
V
IH
1
2.2 - V
CC
+0.3 V
Input Low Voltage
V
IL
2
-0.2 - 0.6 V
Input Leakage Current
I
LI
V
SS
V
IN
V
CC
- 1
-
1
A
Output Leakage Current
I
LO
V
SS
V
I/O
V
CC;
Output Disable
- 1
-
1
A
Output High Voltage
V
OH
I
OH
= -1mA
2.2 2.7
-
V
Output Low Voltage
V
OL
I
OL
= 2.1mA
-
-
0.4
V
55
- 30 40 mA
70
- 20 30 mA
Operating Power
Supply Current
I
CC
Cycle time=min, 100%duty
I/O=0mA, CE =V
IL
100 - 16 25 mA
I
CC1
Tcycle=
1s
- 4 5 mA
Average Operation
Current
I
CC2
100%duty,I
I/O
=0mA, CE
0.2V,
other pins at 0.2V or Vcc-0.2V
Tcycle=
500ns
- 8 10 mA
Standby Current (TTL)
I
SB
CE =V
IH,
other pins =V
IL
or V
IH
- 0.3 0.5 mA
-L
- 20 80 A
Standby Current (CMOS) I
SB1
CE =V
CC
-0.2V
other pins at 0.2V or Vcc-0.2V
-LL
- 2 20 A
Notes:
1. Overshoot : Vcc+2.0v for pulse width less than 10ns.
2. Undershoot : Vss-2.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON
UT62L25716(I)
Rev. 1.3
256K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC.
P80046
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
CAPACITANCE
(T
A
=25
, f=1.0MHz)
PARAMETER
SYMBOL
MIN.
MAX
UNIT
Input Capacitance
C
IN
-
6 pF
Input/Output Capacitance
C
I/O
-
8 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0V to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Reference Levels
1.5V
Output Load
C
L
= 30pF, I
OH
/I
OL
= -1mA/2.1mA
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.7V~3.6V , T
A
= -40
to 85
(I))
(1) READ CYCLE
PARAMETER
SYMBOL
UT62L25716(I)-55 UT62L25716(I)-70 UT62L25716(I)-100
UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time
t
RC
55 - 70 - 100 -
ns
Address Access Time
t
AA
- 55 - 70 - 100
ns
Chip Enable Access Time
t
ACE
- 55 - 70 - 100
ns
Output Enable Access Time
t
OE
- 30 - 35 - 50
ns
Chip Enable to Output in Low Z
t
CLZ*
10 - 10 - 10 -
ns
Output Enable to Output in Low Z
t
OLZ*
5 - 5 - 5 -
ns
Chip Disable to Output in High Z
t
CHZ*
- 20 - 25 - 30
ns
Output Disable to Output in High Z
t
OHZ*
- 20 - 25 - 30
ns
Output Hold from Address Change
t
OH
10 - 10 - 10 -
ns
LB
,
UB
Access Time
t
BA
- 55 - 70 - 100
ns
LB
,
UB
to High-Z Output
t
BHZ
- 25 - 30 - 40
ns
LB
,
UB
to Low-Z Output
t
BLZ
10 - 10 - 10 -
ns
(2) WRITE CYCLE
PARAMETER
SYMBOL
UT62L25716(I)-55 UT62L25716(I)-70 UT62L25716(I)-100
UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Write Cycle Time
t
WC
55 - 70 - 100 -
ns
Address Valid to End of Write
t
AW
50 - 60 - 80 -
ns
Chip Enable to End of Write
t
CW
50 - 60 - 80 -
ns
Address Set-up Time
t
AS
0 - 0 - 0 -
ns
Write Pulse Width
t
WP
45 - 55 - 70 -
ns
Write Recovery Time
t
WR
0 - 0 - 0 -
ns
Data to Write Time Overlap
t
DW
25 - 30 - 40 -
ns
Data Hold from End of Write Time
t
DH
0 - 0 - 0 -
ns
Output Active from End of Write
t
OW*
5 - 5 - 5 -
ns
Write to Output in High Z
t
WHZ*
- 30 - 30 - 40
ns
LB
,
UB
Valid to End of Write
t
BW
45 - 60 - 80 -
ns
* These parameters are guaranteed by device characterization, but not production tested.
UTRON
UT62L25716(I)
Rev. 1.3
256K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC.
P80046
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
6
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
(1,2)
t
RC
t
AA
Data Valid
Address
Dout
t
OH
t
OH
Previous data valid
READ CYCLE 2
(
CE
and
CE2
and
OE
Controlled)
(1,3,4,5)
t
RC
t
AA
t
ACE
t
BLZ
t
OE
t
OHZ
t
CLZ
t
BHZ
t
OH
t
OLZ
High-Z
Data Valid
High-Z
t
BA
t
CHZ
Address
CE2
Dout
CE
LB , UB
OE
Notes :
1.
WE
is high for read cycle.
2.Device is continuously selected OE =low, CE =low
,
CE2=high,
LB
or UB =low
.
3.Address must be valid prior to or coincident with CE =low
,
CE2=high,
LB
or UB =low transition; otherwise t
AA
is the limiting
parameter.
4.t
CLZ
, t
BLZ
, t
OLZ
, t
CHZ
, t
BHZ
and t
OHZ
are specified with C
L
=5pF. Transition is measured
500mV from steady state.
5.At any given temperature and voltage condition, t
CHZ
is less than t
CLZ
, t
BHZ
is less than t
BLZ
, t
OHZ
is less than t
OLZ
.
UTRON
UT62L25716(I)
Rev. 1.3
256K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC.
P80046
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
7
WRITE CYCLE 1
(
WE
Controlled)
(1,2,3,5,6)
t
WC
t
AW
t
CW
t
AS
t
WP
t
BW
t
WHZ
t
OW
t
WR
High-Z
(4)
(4)
Address
CE2
CE
WE
LB , UB
Dout
Din
Data Valid
t
DW
t
DH
WRITE CYCLE 2
(
CE
and CE2
Controlled)
(1,2,5,6)
t
W C
t
A W
t
C W
t
A S
t
W R
t
W P
t
B W
t
W H Z
t
D W
t
D H
Data Valid
High-Z
(4)
Address
CE2
CE
W E
LB , UB
Dout
Din
UTRON
UT62L25716(I)
Rev. 1.3
256K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC.
P80046
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
8
WRITE CYCLE 3
(
LB
, UB
Controlled)
(1,2,5,6)
t
WC
t
AW
t
AS
t
WR
t
CW
t
WP
t
BW
t
WHZ
t
DW
t
DH
Data Valid
Address
CE
CE2
WE
LB , UB
Dout
Din
High-Z
Notes :
1.
WE
, CE ,
LB
, UB must be high or CE2 must be low during all address transitions.
2.A write occurs during the overlap of a low CE , high CE2, low
WE
,
LB
or UB =low.
3.During a
WE
controlled write cycle with OE low, t
WP
must be greater than t
WHZ
+t
DW
to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE ,
LB
, UB low transition and CE2 high transition occurs simultaneously with or after
WE
low transition, the outputs remain in a
high impedance state.
6.t
OW
and t
WHZ
are specified with C
L
= 5pF. Transition is measured
500mV from steady state.
UTRON
UT62L25716(I)
Rev. 1.3
256K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC.
P80046
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
9
DATA RETENTION CHARACTERISTICS
(T
A
= -40
to 85
(I))
PARAMETER
SYMBOL
TEST
CONDITION MIN.
TYP.
MAX.
UNIT
Vcc for Data Retention
V
DR
CE
V
CC
-0.2V or CE2
0.2V
1.5 - 3.6 V
Data Retention Current
I
DR
Vcc=1.5V
- L
-
1
50
A
CE
V
CC
-0.2V
or CE2
0.2V
- LL
-
0.5
20
A
Chip Disable to Data
t
CDR
See Data Retention
0
-
-
ms
Retention Time
Waveforms (below)
Recovery Time
t
R
5
-
-
ms
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1)
(
CE
controlled)
V
DR
1.5V
CE
V
CC
-0.2V
V
cc(min.)
V
cc(min.)
V
IH
V
IH
V
CC
t
R
t
CDR
CE
Low Vcc Data Retention Waveform (2)
(CE2 controlled)
V
DR
1.5V
V
CC(min.)
V
CC
t
R
t
CDR
CE2
0.2V
V
IL
CE2
V
CC(min.)
V
IL
Low Vcc Data Retention Waveform (3)
(
LB
,
UB
controlled)
V
DR
1.5V
LB,UB
V
CC
-0.2V
V
cc(min.)
V
cc(min.)
V
IH
V
IH
V
CC
t
R
t
CDR
LB,UB
UTRON
UT62L25716(I)
Rev. 1.3
256K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC.
P80046
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
10
PACKAGE OUTLINE DIMENSION
48 pin 6.0mmX8.0mm TFBGA Package Outline Dimension
UTRON
UT62L25716(I)
Rev. 1.3
256K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC.
P80046
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
11
ORDERING INFORMATION
INDUSTRIAL TEMPERATURE
PART NO.
ACCESS TIME
( ns )
STANDBY CURRENT
(
A ) typ.
PACKAGE
UT62L25716BS-55LI
55
20
48 PIN BGA
UT62L25716BS-55LLI
55
2
48 PIN BGA
UT62L25716BS-70LI
70
20
48 PIN BGA
UT62L25716BS-70LLI
70
2
48 PIN BGA
UT62L25716BS-100LI
100
20
48 PIN BGA
UT62L25716BS-100LLI
100
2
48 PIN BGA
ORDERING INFORMATION (for lead free product)
INDUSTRIAL TEMPERATURE
PART NO.
ACCESS TIME
( ns )
STANDBY CURRENT
(
A ) typ.
PACKAGE
UT62L25716BSL-55LI
55
20
48 PIN BGA
UT62L25716BSL-55LLI
55
2
48 PIN BGA
UT62L25716BSL-70LI
70
20
48 PIN BGA
UT62L25716BSL-70LLI
70
2
48 PIN BGA
UT62L25716BSL-100LI
100
20
48 PIN BGA
UT62L25716BSL-100LLI
100
2
48 PIN BGA
UTRON
UT62L25716(I)
Rev. 1.3
256K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC.
P80046
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
12
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