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Электронный компонент: UT62L5128LSL-70L

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UTRON
UT62L5128
Rev. 1.4
512K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80051
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
REVISION HISTORY
REVISION DESCRIPTION
Released
DATE
Preliminary Rev. 0.5 Original.
Mar, 2001
Rev. 1.0
1. The symbols CE# and OE# and WE# are revised as. CE and
OE and
WE
.
2. Separate Industrial and Consumer SPEC.
3. Add access time 55ns range.
Jun 21,2001
Rev. 1.1
Add STSOP package
Aug 3,2001
Rev. 1.2
Add SOP package
Mar 25,2002
Rev. 1.3
1. Revised 36-pin TFBGA package outline dimension
a
Rev. 1.2 : ball diameter=0.3mm
b
Rev. 1.3 : ball diameter=0.35mm
2. Revised DC ELECTRICAL CHARACTERISTICS
c
Revised V
IH
as 2.2V
May 3,2002
Rev. 1.4
1. Revised Operation surrent :
-Icc(max)
45/35/25mA 40/30/25mA
-Icc(Typ)
30/25/20mA 30/20/16mA
2. Revised Standby current : 20/3uA 20/2uA
3. Revised V
OH
(Typ) : NA 2.7V
4. Add V
IH
(max)=V
CC
+2.0V for pulse width less than 10ns.
V
IL
(min)=V
SS
-2.0V for pulse width less than 10ns.
5. Revised AC Table t
OHZ*
characteristics
6. Add order information for lead free product
May 8,2003


UTRON
UT62L5128
Rev. 1.4
512K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80051
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
FEATURES
Fast Access time : 55/70/100ns
CMOS Low power operating
Operating current : 40/30/25mA (Icc max.)
Standby current : 20A (typ.) L-version
2A (typ.) LL-version
Single 2.7V~3.6V power supply
Operating Temperature :
Commercial : 0
~70
Extended : -20
~80
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 1.5V (min)
Package : 32-pin 450 mil SOP
32-pin 8mm 20mm TSOP-
32-pin 8mm 13.4mm STSOP
36-pin 6mm 8mm TFBGA
GENERAL DESCRIPTION

The UT62L5128 is a 4,194,304-bit low power CMOS
static random access memory organized as 524,288
words by 8 bits. It is fabricated using high performance,
high reliability CMOS technology.

The UT62L5128 operates from a wide range
2.7V~3.6V power supply and supports extended
operating temperature range.
The UT62L5128 is designed for high density and low
power memory applications. The device has a data
retention mode that guarantees data to remain valid at
a minimum power supply voltage of 1.5V.







FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
512K
8
MEMORY
ARRAY
COLUMN I/O
OE
WE
A0-A18
Vcc
Vss
I/O1-I/O8
CE
UTRON
UT62L5128
Rev. 1.4
512K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80051
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
PIN CONFIGURATION
SOP
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
A17
A8
A9
A11
A10
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
A13
A14
A18
A16
Vcc
A15
29
30
31
32
OE
CE
WE
I/O4
A11
A9
A8
A13
I/O3
A10
A14
A12
A7
A6
A5
Vcc
I/O8
I/O7
I/O6
I/O5
Vss
I/O2
I/O1
A0
A1
A2
A4
A3
TSOP-1 / STSOP
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
A17
A18
A15
32
31
30
29
A16
OE
CE
WE


















A0
NC
A1
A3
A8
A6
I/O5
WE
A2
A4
I/O1
A7
I/O6
NC
A5
I/O2
Vss
Vcc
Vcc
Vss
I/O7
A17
A18
I/O3
I/O8
CE
OE
A16
I/O4
A15
A9
A11
A10
A12
A14
A13
1
2
3
4
5
6
H
G
C
D
E
F
A
B
TFBGA

PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A18
Address Inputs
I/O1 - I/O8
Data Inputs/Outputs
CE
Chip Enable Input
WE
Write Enable Input
OE
Output Enable Input
Vcc Power
Supply
Vss Ground
NC No
Connection
UTRON
UT62L5128
Rev. 1.4
512K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80051
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
SYMBOL
RATING
UNIT
Terminal Voltage with Respect to V
SS
V
TERM
-0.5 to 4.6
V
Commercial T
A
0 to 70
Operating Temperature
Extended T
A
-20 to 80
Storage Temperature
T
STG
-65 to 150
Power Dissipation
P
D
1 W
DC Output Current
I
OUT
50 mA
Soldering Temperature (under 10 secs)
Tsolder
260
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
WE
CE
OE
I/O OPERATION
SUPPLY CURRENT
Standby
X
H
X
High Z
I
SB
, I
SB1
Output Disable
H
L
H
High Z
I
CC
, I
CC1
, I
CC2
Read H
L
L
D
OUT
I
CC
, I
CC1
, I
CC2
Write L
L
X
D
IN
I
CC
, I
CC1
, I
CC2
Note: H = V
IH
, L=V
IL
, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V~3.6V, T
A
=0
to 70
/ -20
to 80
(E))
PARAMETER SYMBOL
TEST
CONDITION
MIN.
TYP.
MAX.
UNIT
Power Voltage
V
CC
2.7
3.0
3.6
V
Input High Voltage
V
IH
*1
2.2 - Vcc+0.3 V
Input Low Voltage
V
IL
2
-
0.2 -
0.6
V
Input Leakage Current
I
LI
V
SS
V
IN
V
CC
-
1
-
1
A
Output Leakage Current
I
LO
V
SS
V
I/O
V
CC,
Output Disable
- 1
-
1
A
Output High Voltage
V
OH
I
OH
= - 1mA
2.2
2.7
-
V
Output Low Voltage
V
OL
I
OL
= 2.1mA
-
-
0.4
V
55 - 30 40 mA
70 - 20 30 mA
Operating Power
Supply Current
I
CC
Cycle time=Min,100% duty
I
I/O
=0mA ,
CE
= V
IL
100
- 16 25 mA
Icc1
TCycle=
1s
- 4 5 mA
Average Operating
Current
Icc2
100% duty, I
I/O=
0mA,
CE
0.2,
other pins at 0.2V or Vcc-0.2V
Tcycle=
500ns
- 8 10 mA
Standby Current(TTL)
I
SB1
CE
=V
IH
,other pins = V
IH
or V
IL
- 0.3 0.5 mA
-L - 20 80 A
Standby Current(CMOS)
I
SB1
CE
V
CC
-0.2V
other pins at 0.2V or Vcc-0.2V
-LL
- 2 20 A
Notes:
1. Overshoot : Vcc+2.0v for pulse width less than 10ns.
2. Undershoot : Vss-2.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON
UT62L5128
Rev. 1.4
512K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80051
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
CAPACITANCE
(T
A
=25
, f=1.0MHz)

PARAMETER
SYMBOL
MIN.
MAX
UNIT
Input Capacitance
C
IN
-
6 pF
Input/Output Capacitance
C
I/O
-
8 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0V to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Reference Levels
1.5V
Output Load
C
L
= 30pF+1TTL, I
OH
/I
OL
= -1mA/2.1mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V~3.6V , T
A
=0
to 70
/ -20
to 80
(E))

(1) READ CYCLE
UT62L5128-55 UT62L5128-70
UT62L5128-100
PARAMETER
SYMBOL
MIN. MAX. MIN. MAX. MIN. MAX.
UNIT
Read Cycle Time
t
RC
55 - 70 - 100
- ns
Address Access Time
t
AA
- 55 - 70 -
100
ns
Chip Enable Access Time
t
ACE
- 55 - 70 -
100
ns
Output Enable Access Time
t
OE
- 30 - 35 - 50
ns
Chip Enable to Output in Low Z
t
CLZ*
10 - 10 - 10 - ns
Output Enable to Output in Low Z
t
OLZ*
5 - 5 - 5 -
ns
Chip Disable to Output in High Z
t
CHZ*
- 20 - 25 - 30
ns
Output Disable to Output in High Z t
OHZ*
- 20 - 25 - 30
ns
Output Hold from Address Change t
OH
10 - 10 - 10 - ns

(2) WRITE CYCLE
UT62L5128-55 UT62L5128-70
UT62L5128-100
PARAMETER SYMBOL
MIN. MAX. MIN. MAX. MIN. MAX.
UNIT
Write Cycle Time
t
WC
55 - 70 - 100
- ns
Address Valid to End of Write
t
AW
50 - 60 - 80 - ns
Chip Enable to End of Write
t
CW
50 - 60 - 80 - ns
Address Set-up Time
t
AS
0 - 0 - 0 -
ns
Write Pulse Width
t
WP
45 - 55 - 70 - ns
Write Recovery Time
t
WR
0 - 0 - 0 -
ns
Data to Write Time Overlap
t
DW
25 - 30 - 40 - ns
Data Hold from End of Write Time
t
DH
0 - 0 - 0 -
ns
Output Active from End of Write
t
OW*
5 - 5 - 5 -
ns
Write to Output in High Z
t
WHZ*
- 30 - 30 - 40
ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON
UT62L5128
Rev. 1.4
512K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80051
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
6
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
(1,2)
t
RC
t
AA
Data Valid
Address
Dout
t
OH
t
OH
Previous data valid

READ CYCLE 2
(
CE
and
OE
Controlled)
(1,3,4,5)
t
RC
t
AA
t
ACE
t
OE
t
OHZ
t
CLZ
t
OH
t
OLZ
High-Z
Data Valid
High-Z
t
CHZ
Address
Dout
CE
OE
Notes :
1.
WE
is high for read cycle.
2.Device is continuously selected OE =low, CE =low
.
3.Address must be valid prior to or coincident with CE =low
,
; otherwise t
AA
is the limiting parameter.
4.t
CLZ
, t
OLZ
, t
CHZ
and t
OHZ
are specified with C
L
=5pF. Transition is measured
500mV from steady state.
5.At any given temperature and voltage condition, t
CHZ
is less than t
CLZ
, t
OHZ
is less than t
OLZ
.
UTRON
UT62L5128
Rev. 1.4
512K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80051
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
7
WRITE CYCLE 1
(
WE
Controlled)
(1,2,3,5,6)
t
WC
t
AW
t
CW
t
AS
t
WP
t
WHZ
t
OW
t
WR
High-Z
(4)
(4)
Address
CE
WE
Dout
Din
Data Valid
t
DW
t
DH
WRITE CYCLE 2
(
CE
Controlled)
(1,2,5,6)
t
W C
t
A W
t
C W
t
A S
t
W R
t
W P
t
W H Z
t
D W
t
D H
Data Valid
High-Z
(4)
Address
CE
W E
Dout
Din
UTRON
UT62L5128
Rev. 1.4
512K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80051
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
8

Notes :
1.
WE
, CE must be high during all address transitions.
2.A write occurs during the overlap of a low CE , low
WE
.
3.During a
WE
controlled write cycle with OE low, t
WP
must be greater than t
WHZ
+t
DW
to allow the drivers to turn off and data to be placed
on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE low transition occurs simultaneously with or after
WE
low transition, the outputs remain in a high impedance state.
6.t
OW
and t
WHZ
are specified with C
L
= 5pF. Transition is measured
500mV from steady state.

DATA RETENTION CHARACTERISTICS
(T
A
=
0
to 70
/ -20
to 80
(E)
)
PARAMETER SYMBOL
TEST
CONDITION
MIN.
TYP.
MAX.
UNIT
Vcc for Data Retention
V
DR
CE
V
CC
-0.2V
1.5 - 3.6 V
Vcc=1.5V
- L
- 1 50
A
Data Retention Current
I
DR
CE
V
CC
-0.2V
- LL
- 0.5 20 A
Chip Disable to Data
Retention Time
t
CDR
See Data Retention
Waveforms (below)
0 - - ms
Recovery Time
t
R
5
-
-
ms

DATA RETENTION WAVEFORM

Low Vcc Data Retention Waveform
(
CE
controlled)
V
DR
1.5V
CE
V
CC
-0.2V
V
cc(min.)
V
cc(min.)
V
IH
V
IH
V
CC
t
R
t
CDR
CE

UTRON
UT62L5128
Rev. 1.4
512K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80051
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
9
PACKAGE OUTLINE DIMENSION
32-pin 450 mil SOP Package Outline Dimension

UNIT
SYMBOL
INCH(BASE) MM(REF)
A
0.118 (MAX)
2.997 (MAX)
A1
0.004 (MIN)
0.102 (MIN)
A2
0.111 (MAX)
2.82 (MAX)
b
0.016 (TYP)
0.406 (TYP)
D
0.817 (MAX)
20.75 (MAX)
E 0.445
0.005 11.303
0.127
E1 0.555
0.012 14.097
0.305
e
0.050 (TYP)
1.270 (TYP)
L 0.0347
0.008 0.881
0.203
L1 0.055
0.008 1.397
0.203
S
0.026 (MAX)
0.660 (MAX)
y
0.004 (MAX)
0.101 (MAX)
0
o
~10
o
0
o
~10
o

UTRON
UT62L5128
Rev. 1.4
512K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80051
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
10
32-pin 8mm x 13.4mm STSOP Package Outline Dimension
1
16
17
32
cL
HD
D
"A"
E
e
Seating Plane
y
32
17
16
1
A2
A1
A
0.254
0
GAUGE PLANE
SEATING PLANE
"A" DATAIL VIEW
L1
b
UNIT
SYMBOL
INCH(BASE) MM(REF)
A
0.047 (MAX)
1.20 (MAX)
A1 0.004
0.002 0.10
0.05
A2 0.039
0.002 1.00
0.05
b 0.008
0.001 0.200
0.025
D 0.465
0.004 11.800
0.100
E 0.315
0.004 8.000
0.100
e
0.020 (TYP)
0.50 (TYP)
HD 0.528
0.008 13.40
0.20.
L1 0.0315
0.004 0.80
0.10
y
0.003 (MAX)
0.076 (MAX)
0
o
5
o
0
o
5
o
UTRON
UT62L5128
Rev. 1.4
512K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80051
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
11
32-pin 8mm x 20mm TSOP-
Package Outline Dimension
HD
e
b
E
"A"
1
16
32
17
Seating Plane
y
CL
16
17
1
32
"A" DETAIL VIEW
D
A2
A1
A
L1
SEATING PLANE
0
0.25
4
GAUGE PLANE
UNIT
SYMBOL
INCH(BASE) MM(REF)
A
0.047 (MAX)
1.20 (MAX)
A1 0.004
0.002 0.10
0.05
A2 0.039
0.002 1.00
0.05
b
0.008 + 0.002
- 0.001
0.20 + 0.05
-0.03
D 0.724
0.004 18.40
0.10
E 0.315
0.004 8.00
0.10
e
0.020 (TYP)
0.50 (TYP)
HD 0.787
0.008 20.00
0.20
L1 0.0315
0.004 0.80
0.10
y
0.003 (MAX)
0.076 (MAX)
0
o
5
o
0
o
5
o

UTRON
UT62L5128
Rev. 1.4
512K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80051
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
12
36-pin 6mm x 8mm TFBGA Package Outline Dimension

UTRON
UT62L5128
Rev. 1.4
512K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80051
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
13
ORDERING INFORMATION

COMMERCIAL TEMPERATURE
PART NO.
ACCESS TIME
(ns)
STANDBY CURRENT
(A) typ.
PACKAGE
UT62L5128SC-55L
55
20
32 PIN SOP
UT62L5128SC-55LL
55
2
32 PIN SOP
UT62L5128SC-70L
70
20
32 PIN SOP
UT62L5128SC-70LL
70
2
32 PIN SOP
UT62L5128LC-55L 55
20
32 PIN TSOP-
UT62L5128LC-55LL 55
2
32 PIN TSOP-
UT62L5128LC-70L 70
20
32 PIN TSOP-
UT62L5128LC-70LL 70
2
32 PIN TSOP-
UT62L5128LS-55L
55
20
32 PIN STSOP
UT62L5128LS-55LL
55
2
32 PIN STSOP
UT62L5128LS-70L
70
20
32 PIN STSOP
UT62L5128LS-70LL
70
2
32 PIN STSOP
UT62L5128BS-55L
55
20
36 PIN TFBGA
UT62L5128BS-55LL
55
2
36 PIN TFBGA
UT62L5128BS-70L
70
20
36 PIN TFBGA
UT62L5128BS-70LL
70
2
36 PIN TFBGA

EXTENDED TEMPERATURE
PART NO.
ACCESS TIME
(ns)
STANDBY CURRENT
(A) typ.
PACKAGE
UT62L5128SC-55LE
55
20
32 PIN SOP
UT62L5128SC-55LLE
55
2
32 PIN SOP
UT62L5128SC-70LE
70
20
32 PIN SOP
UT62L5128SC-70LLE
70
2
32 PIN SOP
UT62L5128LC-55LE 55
20
32 PIN TSOP-
UT62L5128LC-55LLE 55
2
32 PIN TSOP-
UT62L5128LC-70LE 70
20
32 PIN TSOP-
UT62L5128LC-70LLE 70
2
32 PIN TSOP-
UT62L5128LS-55LE
55
20
32 PIN STSOP
UT62L5128LS-55LLE
55
2
32 PIN STSOP
UT62L5128LS-70LE
70
20
32 PIN STSOP
UT62L5128LS-70LLE
70
2
32 PIN STSOP
UT62L5128BS-55LE
55
20
36 PIN TFBGA
UT62L5128BS-55LLE
55
2
36 PIN TFBGA
UT62L5128BS-70LE
70
20
36 PIN TFBGA
UT62L5128BS-70LLE
70
2
36 PIN TFBGA
UTRON
UT62L5128
Rev. 1.4
512K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80051
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
14
ORDERING INFORMATION (for lead free product)

COMMERCIAL TEMPERATURE
PART NO.
ACCESS TIME
(ns)
STANDBY CURRENT
(A) typ.
PACKAGE
UT62L5128SCL-55L
55
20
32 PIN SOP
UT62L5128SCL-55LL
55
2
32 PIN SOP
UT62L5128SCL-70L
70
20
32 PIN SOP
UT62L5128SCL-70LL
70
2
32 PIN SOP
UT62L5128LCL-55L 55
20
32 PIN TSOP-
UT62L5128LCL-55LL 55
2
32 PIN TSOP-
UT62L5128LCL-70L 70
20
32 PIN TSOP-
UT62L5128LCL-70LL 70
2
32 PIN TSOP-
UT62L5128LSL-55L
55
20
32 PIN STSOP
UT62L5128LSL-55LL
55
2
32 PIN STSOP
UT62L5128LSL-70L
70
20
32 PIN STSOP
UT62L5128LSL-70LL
70
2
32 PIN STSOP
UT62L5128BSL-55L
55
20
36 PIN TFBGA
UT62L5128BSL-55LL
55
2
36 PIN TFBGA
UT62L5128BSL-70L
70
20
36 PIN TFBGA
UT62L5128BSL-70LL
70
2
36 PIN TFBGA

EXTENDED TEMPERATURE
PART NO.
ACCESS TIME
(ns)
STANDBY CURRENT
(A) typ.
PACKAGE
UT62L5128SCL-55LE
55
20
32 PIN SOP
UT62L5128SCL-55LLE
55
2
32 PIN SOP
UT62L5128SCL-70LE
70
20
32 PIN SOP
UT62L5128SCL-70LLE
70
2
32 PIN SOP
UT62L5128LCL-55LE 55
20
32 PIN TSOP-
UT62L5128LCL-55LLE 55
2 32 PIN TSOP-
UT62L5128LCL-70LE 70
20
32 PIN TSOP-
UT62L5128LCL-70LLE 70
2 32 PIN TSOP-
UT62L5128LSL-55LE
55
20
32 PIN STSOP
UT62L5128LSL-55LLE
55
2
32 PIN STSOP
UT62L5128LSL-70LE
70
20
32 PIN STSOP
UT62L5128LSL-70LLE
70
2
32 PIN STSOP
UT62L5128BSL-55LE
55
20
36 PIN TFBGA
UT62L5128BSL-55LLE
55
2
36 PIN TFBGA
UT62L5128BSL-70LE
70
20
36 PIN TFBGA
UT62L5128BSL-70LLE
70
2
36 PIN TFBGA
UTRON
UT62L5128
Rev. 1.4
512K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80051
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
15



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