UTRON
UT62L51316(I)
Preliminary Rev. 0.1
512K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC.
P80086
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
REVISION HISTORY
REVISION DESCRIPTION
Draft
Date
Preliminary Rev. 0.1 Original.
Apr. 15, 2003
UTRON
UT62L51316(I)
Preliminary Rev. 0.1
512K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC.
P80086
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
FEATURES
Fast access time : 55/70/100ns
CMOS low power operating
Operating current : 30/20/16 (Icc) (TYP.)
Standby current : 20uA (TYP.) L-version
2uA (TYP.) LL-version
Single 2.7V~3.6V power supply
Operation temperature:
Industrial : -40
~85
All TTL compatible inputs and outputs
Fully static operation
Three state outputs
Data retention voltage:1.5V (min.)
Data byte control : LB (I/O1~I/O8)
UB (I/O9~I/O16)
Package : 48-pin 12mmX20mm TSOP-I
48-ball 6mm 8mm TFBGA
GENERAL DESCRIPTION
The UT62L51316(I) is a 8,388,608-bit low power
CMOS static random access memory organized as
524,288 words by 16 bits.
The UT62L51316(I) operates from a single 2.7V ~
3.6V power supply and all inputs and outputs are fully
TTL compatible.
The UT62L51316(I) is designed for low power system
applications. It is particularly well suited for use in
high-density low power system applications.
FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
512K
16
MEMORY
ARRAY
COLUMN I/O
A0-A18
Vcc
Vss
I/O1-I/O8
Lower Byte
I/O9-I/O16
Upper Byte
CE2
OE
W E
LB
UB
CE
UTRON
UT62L51316(I)
Preliminary Rev. 0.1
512K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80086
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
PIN CONFIGURATION
TSOP-I
I/O7
Vss
I/O14
I/O13
I/O6
I/O12
I/O5
Vcc
I/O4
I/O11
A16
Vss
I/O2
I/O9
I/O3
I/O1
I/O10
I/O8
I/O15
35
36
37
38
39
40
41
42
43
44
45
46
48
32
33
34
29
30
31
27
28
47
25
26
I/O16
A0
CE
OE
14
13
12
11
10
9
8
7
6
5
4
3
1
17
16
15
20
19
18
22
21
2
24
23
NC
UT62L51316(I)
A12
A13
A14
A15
A9
A8
NC
CE2
A7
NC
NC
A6
A11
A5
A4
A3
A10
A17
A2
A1
WE
LB
UB
A18
L B
A 0
O E
A 1
C E 2
A 2
I /O 9
A 3
U B
A 4
I /O 1
C E
I /O 1 0
A 5
I /O 1 1
A 6
I /O 3
I /O 2
V s s
A 1 7
I /O 1 2
A 7
V c c
I /O 4
V c c
N C
I /O 1 3
A 1 6
V s s
I /O 5
I /O 1 5
A 1 4
I /O 1 4
A 1 5
I /O 7
I /O 6
I /O 1 6
A 1 2
N C
A 1 3
I /O 8
W E
A 1 8
A 9
A 8
A 1 0
N C
A 1 1
1
2
3
4
5
6
H
G
C
D
E
F
A
B
T F B G A
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0 - A18
Address Inputs
I/O1 - I/O16 Data Inputs/Outputs
CE , CE2
Chip Enable Input
WE
Write Enable Input
OE
Output Enable Input
LB
Lower-byte Control
UB
Upper-byte Control
V
CC
Power
Supply
V
SS
Ground
NC No
Connection
TRUTH TABLE
I/O OPERATION
MODE
CE
CE2
OE
WE
LB
UB
I/O1-I/O8 I/O9-I/O16
SUPPLY
CURRENT
Standby
H
X
X
X
L
X
X
X
X
X
X
X
X
X
H
X
X
H
High Z
High Z
High Z
High Z
High Z
High Z
I
SB
, I
SB1
Output Disable
L
L
H
H
H
H
H
H
L
X
X
L
High Z
High Z
High Z
High Z
I
CC
,I
CC1
, I
CC2
Read
L
L
L
H
H
H
L
L
L
H
H
H
L
H
L
H
L
L
D
OUT
High Z
D
OUT
High Z
D
OUT
D
OUT
I
CC
,I
CC1
, I
CC2
Write
L
L
L
H
H
H
X
X
X
L
L
L
L
H
L
H
L
L
D
IN
High Z
D
IN
High Z
D
IN
D
IN
I
CC
,I
CC1
, I
CC2
Note: H = V
IH
, L=V
IL
, X = Don't care.
UTRON
UT62L51316(I)
Preliminary Rev. 0.1
512K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80086
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
ABSOLUTE MAXIMUM RATINGS*
PARAMETER SYMBOL
RATING
UNIT
Terminal Voltage with Respect to V
SS
V
TERM
-0.5 to 4.6
V
Operating Temperature
Industrial
T
A
-40 to 85
Storage Temperature
T
STG
-65 to 150
Power Dissipation
P
D
1
W
DC Output Current
I
OUT
50
mA
Soldering Temperature (under 10 secs)
Tsolder
260
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(Vcc = 2.7V~3.6V, T
A
= -40
to 85
(I))
PARAMETER
SYMBOL
TEST CONDITION
MIN. TYP. MAX. UNIT
Power Voltage
V
CC
2.7 3.0 3.6 V
Input High Voltage
V
IH
*1
2.2 - V
CC
+0.3 V
Input Low Voltage
V
IL
*2
-0.2 - 0.6 V
Input Leakage Current
I
LI
V
SS
V
IN
V
CC
- 1
-
1
A
Output Leakage Current
I
LO
V
SS
V
I/O
V
CC;
Output Disable
- 1
-
1
A
Output High Voltage
V
OH
I
OH
= -1mA
2.2 2.7
-
V
Output Low Voltage
V
OL
I
OL
= 2.1mA
-
-
0.4
V
55
- 30 40 mA
70
- 20 30 mA
Operating Power
Supply Current
I
CC
Cycle time=min, 100%duty
I/O=0mA, CE =V
IL
, CE2=V
IH
,
LB or UB =V
IL
100
- 16 25 mA
I
CC1
Cycle time=1s, 100% duty, I
I/O
=0mA,
CE
0.2V,CE2
V
CC
-0.2V, LB or UB
0.2V,
other pins at 0.2V or Vcc-0.2V
- 4 5 mA
Average Operation
Current
I
CC2
Cycle time=500ns, 100% duty, I
I/O
=0mA,
CE
0.2V,CE2
V
CC
-0.2V, LB or UB
0.2V,
other pins at 0.2V or Vcc-0.2V
- 8 10 mA
Standby Current (TTL)
I
SB
CE =V
IH
, or CE2=V
IL
, or LB = UB =V
IH
- 0.3 0.5 mA
-L
- 20 80 A
Standby Current (CMOS) I
SB1
CE
V
CC
-0.2V, or CE2
0.2V,
or LB = UB =V
CC
-0.2V,
-LL
- 2 20 A
Notes:
1. Overshoot : Vcc+2.0v for pulse width less than 10ns.
2. Undershoot : Vss-2.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON
UT62L51316(I)
Preliminary Rev. 0.1
512K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80086
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
CAPACITANCE (T
A
=25
, f=1.0MHz)
PARAMETER
SYMBOL
MIN.
MAX
UNIT
Input Capacitance
C
IN
-
6 pF
Input/Output Capacitance
C
I/O
-
8 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0.1V
CC
to 0.9V
CC
Input Rise and Fall Times
5ns
Input and Output Timing Reference Levels
1.5V
Output Load
C
L
= 30pF+1 TTL, I
OH
/I
OL
= -1mA/2.1mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V~3.6V , T
A
= -40
to 85
(I))
(1) READ CYCLE
UT62L51316(I)-55 UT62L51316(I)-70 UT62L51316(I)-100
PARAMETER SYMBOL
MIN. MAX. MIN. MAX. MIN. MAX.
UNIT
Read Cycle Time
t
RC
55 - 70 - 100 -
ns
Address Access Time
t
AA
- 55 - 70 - 100
ns
Chip Enable Access Time
t
ACE
- 55 - 70 - 100
ns
Output Enable Access Time
t
OE
- 30 - 35 - 50
ns
Chip Enable to Output in Low Z
t
CLZ
*
10 - 10 - 10 -
ns
Output Enable to Output in Low Z
t
OLZ
*
5 - 5 - 5 -
ns
Chip Disable to Output in High Z
t
CHZ
*
- 20 - 25 - 30
ns
Output Disable to Output in High Z
t
OHZ
*
- 20 - 25 - 30
ns
Output Hold from Address Change
t
OH
10 - 10 - 10 -
ns
LB
,
UB
Access Time
t
BA
- 55 - 70 - 100
ns
LB
,
UB
to High-Z Output
t
BHZ
*
- 20 - 25 - 30
ns
LB
,
UB
to Low-Z Output
t
BLZ
*
10 - 10 - 10 -
ns
(2) WRITE CYCLE
UT62L51316(I)-55 UT62L51316(I)-70 UT62L51316(I)-100
PARAMETER SYMBOL
MIN. MAX. MIN. MAX. MIN. MAX.
UNIT
Write Cycle Time
t
WC
55 - 70 - 100 -
ns
Address Valid to End of Write
t
AW
50 - 60 - 80 -
ns
Chip Enable to End of Write
t
CW
50 - 60 - 80 -
ns
Address Set-up Time
t
AS
0 - 0 - 0 -
ns
Write Pulse Width
t
WP
45 - 55 - 70 -
ns
Write Recovery Time
t
WR
0 - 0 - 0 -
ns
Data to Write Time Overlap
t
DW
25 - 30 - 40 -
ns
Data Hold from End of Write Time
t
DH
0 - 0 - 0 -
ns
Output Active from End of Write
t
OW
*
5 - 5 - 5 -
ns
Write to Output in High Z
t
WHZ
*
- 20 - 25 - 30
ns
LB
,
UB
Valid to End of Write
t
BW
50 - 60 - 80 -
ns
* These parameters are guaranteed by device characterization, but not production tested.
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