UTRON
UT62L6416(I)
Rev. 1.1
64K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80093
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
REVISION HISTORY
REVISION DESCRIPTION
Released
Date
Rev. 1.0
Original.
Jul 25. 2002
Rev. 1.1
Add order information for lead free product
May 08. 2003
UTRON
UT62L6416(I)
Rev. 1.1
64K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80093
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
FEATURES
Fast access time : 55/70ns
CMOS Low power operating
Operating current: 35/25mA (Icc max)
Standby current: 2uA(TYP.) LL-version
Single 2.7V~3.6V power supply
Operating temperature:
Industrial : -40
~85
All TTL compatible inputs and outputs
Fully static operation
Three state outputs
Data retention voltage: 1.5V (min)
Data byte control :
LB
(I/O1~I/O8)
UB (I/O9~I/O16)
Package : 44-pin 400mil TSOP
48-pin 6mm 8mm TFBGA
GENERAL DESCRIPTION
The UT62L6416 is a 1,048,576-bit low power CMOS
static random access memory organized as 65,536
words by 16 bits.
The UT62L6416 operates from a single 2.7V ~ 3.6V
power supply and all inputs and outputs are fully TTL
compatible.
The UT62L6416 is design for upper and lower byte
access by data byte control ( UB
LB
).
FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
64Kx16
MEMORY
ARRAY
COLUMN I/O
CE
OE
WE
A0-A15
Vcc
Vss
I/O1-I/O8
Lower Byte
I/O9-I/O16
Upper Byte
UB
LB
UTRON
UT62L6416(I)
Rev. 1.1
64K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80093
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
PIN CONFIGURATION
TSOP II
A1
A2
A3
A4
I/O16
I/O1
I/O2
I/O3
Vcc
Vss
NC
A15
I/O15
I/O13
I/O14
I/O12
Vss
Vcc
I/O11
I/O10
I/O4
I/O5
UT62L6416
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
CE
OE
A14
A0
I/O7
I/O8
A5
A6
A7
A8
A9
I/O6
I/O9
A13
A12
NC
A10
WE
NC
34
29
30
31
32
33
44
39
40
41
42
43
35
36
37
38
UB
LB
A11
OE
CE
WE
LB
UB
A12
A11
A13
NC
I/O9
A10
A14
I/O11
I/O10
A15
I/O6
I/O7
I/O8
A9
Vss
I/O12
A8
NC
I/O5
Vcc
Vcc
I/O4
NC
NC
I/O13
Vss
NC
A7
A0
I/O3
I/O2
I/O15
I/O14
I/O1
NC
A6
A1
A3
A5
NC
I/O16
A4
A2
1
2
3
4
5
6
H
G
C
D
E
F
A
B
TFBGA
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A15
Address Inputs
I/O1 - I/O16
Data Inputs/Outputs
CE
Chip Enable Input
WE
Write Enable Input
OE
Output Enable Input
LB
Lower-Byte Control
UB
Upper-Byte Control
V
CC
Power
Supply
V
SS
Ground
NC No
Connection
UTRON
UT62L6416(I)
Rev. 1.1
64K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80093
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
TRUTH TABLE
I/O OPERATION
MODE
CE
OE
WE
LB
UB
I/O1-I/O8 I/O9-I/O16
SUPPLY CURRENT
H
X
X
X
X
High Z
High Z
I
SB
, I
SB1
Standby
X
X
X
H
H
High Z
High Z
I
SB
, I
SB1
Output
Disable
L
L
H
H
H
H
L
X
X
L
High Z
High Z
High Z
High Z
I
CC
,I
CC1
,I
CC2
Read L
L
L
L
L
L
H
H
H
L
H
L
H
L
L
D
OUT
High Z
D
OUT
High Z
D
OUT
D
OUT
I
CC
,I
CC1
,I
CC2
Write L
L
L
X
X
X
L
L
L
L
H
L
H
L
L
D
IN
High Z
D
IN
High Z
D
IN
D
IN
I
CC
,I
CC1
,I
CC2
Note: H = V
IH
, L=V
IL
, X = Don't care.
ABSOLUTE MAXIMUM RATINGS*
PARAMETER SYMBOL
RATING
UNIT
Terminal Voltage with Respect to V
SS
V
TERM
-0.5 to 4.6
V
Operating Temperature
Industrial
T
A
-40 to 85
Storage Temperature
T
STG
-65 to 150
Power Dissipation
P
D
1
W
DC Output Current
I
OUT
50
mA
Soldering Temperature (under 10 secs)
Tsolder
260
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V~3.6V, T
A
= -40
to 85
)
PARAMETER SYMBOL
TEST
CONDITION
MIN.
TYP.
MAX.
UNIT
Power Voltage
V
CC
2.7 3.0 3.6 V
Input High Voltage
V
IH
*1
2.2 -
V
CC
+0.3 V
Input Low Voltage
V
IL
*2
-0.2 - 0.6 V
Input Leakage Current
I
LI
V
SS
V
IN
V
CC
- 1
-
1
A
Output Leakage Current
I
LO
V
SS
V
I/O
V
CC;
Output Disabled
- 1
-
1
A
Output High Voltage
V
OH
I
OH
= -1mA
2.2 - - V
Output Low Voltage
V
OL
I
OL
= 2.1mA
- - 0.4
V
55
- 25 35 mA
Operating Power
Supply Current
I
CC
Cycle time=min, 100%duty,
I/O=0mA,
CE
=V
IL
;
70
- 20 25 mA
Icc1 Tcycle=
1s
- 4 5 mA
Average Operation
Current
Icc2
100%duty,I
I/O
=0mA,
CE
0.2V,other pins at 0.2V or
Vcc-0.2V,
Tcycle=
500ns
- 8 10
mA
Standby Current (TTL)
I
SB
1.
CE
=V
IH,
other pins =V
IL
or V
IH
,
2.
UB
=
LB
= V
IH,
other pins =V
IL
or V
IH
,
- 0.3 0.5 mA
Standby Current (CMOS)
I
SB1
1.
CE
=V
CC
-0.2V,
other pins at 0.2V or Vcc-0.2V,
2.
UB
=
LB
=V
CC
-0.2V,
other pins at 0.2V or Vcc-0.2V,
-LL
- 2 10
A
Notes:
1. Overshoot : Vcc+3.0v for pulse width less than 10ns.
2. Undershoot : Vss-3.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON
UT62L6416(I)
Rev. 1.1
64K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80093
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
CAPACITANCE (TA=25
, f=1.0MHz)
PARAMETER
SYMBOL
MIN.
MAX
UNIT
Input Capacitance
C
IN
-
6 pF
Input/Output Capacitance
C
I/O
-
8 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0V to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Reference Levels
1.5V
Output Load
C
L
= 30pF, I
OH
/I
OL
= -1mA / 2.1mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
=2.7V~3.6V, TA = -40
to 85
)
(1) READ CYCLE
PARAMETER
SYMBOL
UT62L6416(I)-55 UT62L6416(I)-70
UNIT
MIN. MAX. MIN. MAX.
Read Cycle Time
t
RC
55 - 70 - ns
Address Access Time
t
AA
-
55
- 70 ns
Chip Enable Access Time
t
ACE
- 55 - 70 ns
Output Enable Access Time
t
OE
- 30
- 35 ns
Chip Enable to Output in Low Z
t
CLZ*
10 - 10 - ns
Output Enable to Output in Low Z
t
OLZ*
5 - 5 - ns
Chip Disable to Output in High Z
t
CHZ*
- 20 - 25 ns
Output Disable to Output in High Z
t
OHZ*
- 20 - 25 ns
Output Hold from Address Change
t
OH
10 - 10 - ns
LB
,
UB
Access Time
t
BA
-
55
- 70 ns
LB
,
UB
to High-Z Output
t
BHZ
- 25 - 30 ns
LB
,
UB
to Low-Z Output
t
BLZ
10 - 10 - ns
(2) WRITE CYCLE
PARAMETER
SYMBOL
UT62L6416(I)-55 UT62L6416(I)-70
UNIT
MIN. MAX. MIN. MAX.
Write Cycle Time
t
WC
55 - 70 - ns
Address Valid to End of Write
t
AW
50 - 60 - ns
Chip Enable to End of Write
t
CW
50 - 60 - ns
Address Set-up Time
t
AS
0 - 0 - ns
Write Pulse Width
t
WP
45 - 55 - ns
Write Recovery Time
t
WR
0 - 0 - ns
Data to Write Time Overlap
t
DW
25 - 30 - ns
Data Hold from End of Write Time
t
DH
0 - 0 - ns
Output Active from End of Write
t
OW*
5 - 5 - ns
Write to Output in High Z
t
WHZ*
- 30 - 30 ns
LB
,
UB
Valid to End of Write
t
BW
45 - 60 - ns
*These parameters are guaranteed by device characterization, but not production tested.
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