UTRON
UT62L64C
Rev. 1.3
8K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY
REVISION DESCRIPTION
Released
Date
Rev. 0.1
Original
May 3,2001
Rev. 1.0
Release
Feb.26,2002
Rev. 1.1
Revised
-
Improve I
DR
from 20
A to 10
A (LL-version , max.)
May 14,2002
Rev. 1.2
1. Revised Single power supply : 3.3V 3.0V~3.6V
2. Add Extended temperature : -20
~85
3. Revised "Order information" : add Extended parts
4. AC/DC characteristics :
-add Extended temperature
-Icc1 (TYP):12 6mA, Icc1 (MAX) : 20 10mA
-Icc2 (TYP):6 12mA, Icc2(MAX) : 10 20mA
Jul 30,2002
Rev. 1.3
Add order information for lead free product
May 15,2003
UTRON TECHNOLOGY INC. P80060
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
UTRON
UT62L64C
Rev. 1.3
8K X 8 BIT LOW POWER CMOS SRAM
FEATURES
Access time : 35/70ns (max.)
Low power consumption:
Operating : 30/20 mA (typical)
Standby :
1.5mA (typical) normal
1
A (typical) L-version
0.5
A (typical) LL-version
Single 3.0V~3.6V power supply
Operating temperature :
Commerical : 0
~70
Extended : -20
~85
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 1.5V (min.)
Package : 28-pin 600mil PDIP
28-pin 330 mil SOP
Substrate connected : Vcc
FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
8K
8
MEMORY
ARRAY
COLUMN I/O
OE
WE
A0-A12
Vcc
Vss
I/O1-I/O8
CE
CE2
GENERAL DESCRIPTION
The UT62L64C is a 65,536-bits low power
CMOS static random access memory organized
as 8,192 words by 8 bits. It is fabricated using
high performance, high reliability CMOS
technology.
Easy memory expansion is provided by using
two chip enable input.( CE ,CE2) The
UT62L64C operates from a single 3.3V power
supply and all inputs and outputs are fully TTL
compatible.
PIN CONFIGURATION
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
Vcc
A8
A9
A11
A10
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
UT62L64C
SOP/PDIP
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
WE
OE
CE2
NC
CE
PAD DESCRIPTION
SYMBOL DESCRIPTION
A0 - A12
Address Inputs
I/O1 - I/O8
Data Inputs/Outputs
CE ,CE2
Chip Enable Inputs
WE
Write Enable Input
OE
Output Enable Input
V
CC
Power
Supply
V
SS
Ground
NC
UTRON TECHNOLOGY INC. P80060
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
UTRON
UT62L64C
Rev. 1.3
8K X 8 BIT LOW POWER CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER SYMBOL
RATING
UNIT
Terminal Voltage with Respect to V
SS
V
TERM
-0.5 to 4.5
V
Commerical T
A
0 to 70
Operating Temperature
Extended T
A
-20 to 85
Storage Temperature
T
STG
-65 to 150
Power Dissipation
P
D
1
W
DC Output Current
I
OUT
50
mA
Soldering Temperature (under 10 sec)
Tsolder
260
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect
device reliability.
TRUTH TABLE
MODE
CE
CE2
OE
WE
I/O OPERATION
SUPPLY CURRENT
Standby
H
X
X
X
High - Z
I
SB,
I
SB1
Standby
X L X X
High
-
Z
I
SB,
I
SB1
Output Disable
L
H
H
H
High - Z
I
CC,
I
CC1,
I
CC2
Read
L H L H
D
OUT
I
CC,
I
CC1,
I
CC2
Write L
H
X
L D
IN
I
CC,
I
CC1,
I
CC2
note: H = V
IH
, L=V
IL
, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 3.0~3.6V, T
A
= 0
to 70
/ -20
to 85
(E))
PARAMETER SYMBOL TEST
CONDITION
MIN.
TYP.
MAX.
UNIT
Input High Voltage
V
IH
1
2.2
-
VCC+0.5
V
Input Low Voltage
V
IL
2
-
0.5
-
0.6
V
Input Leakage Current
I
LI
V
SS
V
IN
V
CC
- 1
-
1
A
Output Leakage
Current
I
LO
V
SS
V
I/O
V
CC
CE
= V
IH
or CE2= V
IL
or
OE
= V
IH
or
WE
= V
IL
- 1
-
1
A
Output High Voltage
V
OH
I
OH
= - 1mA
2.4
-
-
V
Output Low Voltage
V
OL
I
OL
= 4mA
-
-
0.4
V
- 35
-
30
40
mA
I
CC
Cycle time=Min,I
I/O
= 0mA
CE
= V
IL
, CE2= V
IH
- 70
-
20
30
mA
Icc1
CE
=0.2V; I
I/O
= 0mA other pins
at 0.2V or Vcc-0.2V;
TCycle
=1us
- 6 10 mA
Operating Power
Supply Current
Icc2
CE
=0.2V; I
I/O
= 0mA
other pins at 0.2V or Vcc-0.2V
TCycle
=500ns
- 12 20 mA
Normal - 1 10 mA
Standby Current (TTL)
I
SB
CE
= V
IH
or CE2= V
IL
other pins=V
IL
or V
IH
- L/- LL
-
0.3
3
mA
Normal - 1.5 5 mA
- L
1
100
A
Standby current
(CMOS)
I
SB
1
CE
V
CC
-0.2V
or CE2
0.2V ,
other pins at 0.2V or Vcc-0.2V
- LL
-
0.5
50
A
Notes:
1. Overshoot : Vcc+3.0v for pulse width less than 10ns.
2. Undershoot : Vss-3.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON TECHNOLOGY INC. P80060
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
UTRON
UT62L64C
Rev. 1.3
8K X 8 BIT LOW POWER CMOS SRAM
C
APACITANCE (T
A
=25
, f=1.0MHz)
PARAMETER SYMBOL
MIN.
MAX
UNIT
Input Capacitance
C
IN
-
8 pF
Input/Output Capacitance
C
I/O
-
10 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
A
C TEST CONDITIONS
Input Pulse Levels
0V to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Reference Levels
1.5V
Output Load
C
L
= 100pF, I
OH
/I
OL
= -1mA/4 mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 3.0~3.6V, T
A
= 0
to 70
/ -20
to 85
(E))
(1) READ CYCLE
UT62L64C-35 UT62L64C-70
PARAMETER
SYMBOL
MIN. MAX. MIN. MAX.
UNIT
Read Cycle Time
t
RC
35 - 70 - ns
Address Access Time
t
AA
- 35 - 70 ns
Chip Enable Access Time
t
ACE
- 35 - 70 ns
Output Enable Access Time
t
OE
- 25 - 35 ns
Chip Enable to Output in Low-Z
t
CLZ*
10 - 10 - ns
Output Enable to Output in Low-Z
t
OLZ*
5 - 5 - ns
Chip Disable to Output in High-Z
t
CHZ*
- 25 - 35 ns
Output Disable to Output in High-Z
t
OHZ*
- 25 - 35 ns
Output Hold from Address Change
t
OH
5 - 5 - ns
(2) WRITE CYCLE
UT62L64C-35 UT62L64C-70
PARAMETER SYMBOL
MIN. MAX. MIN. MAX.
UNIT
Write Cycle Time
t
WC
35 - 70 - ns
Address Valid to End of Write
t
AW
30 - 60 - ns
Chip Enable to End of Write
t
CW
30 - 60 - ns
Address Set-up Time
t
AS
0 - 0 - ns
Write Pulse Width
t
WP
25 - 50 - ns
Write Recovery Time
t
WR
0 - 0 - ns
Data to Write Time Overlap
t
DW
20 - 30 - ns
Data Hold from End of Write-Time
t
DH
0 - 0 - ns
Output Active from End of Write
t
OW*
5 - 5 - ns
Write to Output in High-Z
t
WHZ*
- 15 - 25 ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC. P80060
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
UTRON
UT62L64C
Rev. 1.3
8K X 8 BIT LOW POWER CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
(1,2)
t
RC
t
AA
Data Valid
Address
Dout
t
OH
t
OH
Previous data valid
READ CYCLE 2
(
CE
and
CE2
and
OE
Controlled)
(1,3,4,5)
t
RC
t
AA
t
ACE
t
OE
t
OHZ
t
CLZ
t
OH
t
OLZ
High-Z
Data Valid
High-Z
t
CHZ
Address
CE2
Dout
CE
OE
Notes :
1.
WE
is high for read cycle.
2.Device is continuously selected OE =low, CE =low
,
CE2=high
.
3.Address must be valid prior to or coincident with CE =low
,
CE2=high; otherwise t
AA
is the limiting parameter.
4.t
CLZ
, t
OLZ
, t
CHZ
and t
OHZ
are specified with C
L
=5pF. Transition is measured
500mV from steady state.
5.At any given temperature and voltage condition, t
CHZ
is less than t
CLZ,,
t
OHZ
is less than t
OLZ
.
UTRON TECHNOLOGY INC. P80060
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
UTRON
UT62L64C
Rev. 1.3
8K X 8 BIT LOW POWER CMOS SRAM
WRITE CYCLE 1
(
WE
Controlled)
(1,2,3,5,6)
t
WC
t
AW
t
CW
t
AS
t
WP
t
WHZ
t
OW
t
WR
High-Z
(4)
(4)
Address
CE2
CE
WE
Dout
Din
Data Valid
t
DW
t
DH
WRITE CYCLE 2
(
CE
and CE2
Controlled)
(1,2,5,6)
t
W C
t
A W
t
C W
t
A S
t
W R
t
W P
t
W H Z
t
D W
t
D H
Data Valid
High-Z
(4)
Address
CE2
CE
W E
Dout
Din
UTRON TECHNOLOGY INC. P80060
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
6
UTRON
UT62L64C
Rev. 1.3
8K X 8 BIT LOW POWER CMOS SRAM
Notes :
1.
WE
, CE must be high or CE2 must be low during all address transitions.
2.A write occurs during the overlap of a low CE , high CE2, low
WE
.
3.During a
WE
controlled write cycle with OE low, t
WP
must be greater than t
WHZ
+t
DW
to allow the drivers to turn off and data to
be placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE low transition and CE2 high transition occurs simultaneously with or after
WE
low transition, the outputs remain in a
high impedance state.
6.t
OW
and t
WHZ
are specified with C
L
= 5pF. Transition is measured
500mV from steady state.
DATA RETENTION CHARACTERISTICS
(T
A
= 0
to 70
/ -20
to 85
(E))
PARAMETER SYMBOL
TEST
CONDITION
MIN.
TYP.
MAX.
UNIT
Vcc for Data Retention
V
DR
CE
V
CC
-0.2V or CE2
0.2V
1.5 - 3.6 V
-L
- 1 50
A
Data Retention Current
I
DR
Vcc=2.5V
CE
V
CC
-0.2V
or CE2
0.2V
-LL
- 0.5 10
A
Chip Disable to Data
Retention Time
t
CDR
See Data Retention Waveforms
(below)
0 - - ns
Recovery Time
t
R
t
RC*
- - ns
t
RC*
= Read Cycle Time
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1)
(
CE
controlled)
V
DR
1.5V
CE
V
CC
-0.2V
V
cc(min.)
V
cc(min.)
V
IH
V
IH
V
CC
t
R
t
CDR
CE
Low Vcc Data Retention Waveform (2)
(CE2 controlled)
V
DR
1.5V
V
CC(min.)
V
CC
t
R
t
CDR
CE2
0.2V
V
IL
CE2
V
CC(min.)
V
IL
UTRON TECHNOLOGY INC. P80060
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
7
UTRON
UT62L64C
Rev. 1.3
8K X 8 BIT LOW POWER CMOS SRAM
PACKAGE OUTLINE DIMENSION
28 pin 600 mil PDIP Package Outline Dimension
UNIT
SYMBOL
INCH(BASE) MM(REF)
A1 0.010(MIN) 0.254(MIN)
A2
0.150
0.001 3.810
0.254
B
0.018
0.005 0.457
0.127
c
0.010
0.004 0.254
0.102
D
1.460
0.005 37.084
0.127
E
0.600
0.010 15.240
0.254
e 0.100
(TYP)
2.540(TYP)
eB
0.640
0.03 16.256
0.762
L
0.130
0.010 3.302
0.254
0
o
~15
o
0
o
~15
o
UTRON TECHNOLOGY INC. P80060
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
8
UTRON
UT62L64C
Rev. 1.3
8K X 8 BIT LOW POWER CMOS SRAM
28 pin 330 mil SOP Package Outline Dimension
UNIT
SYMBOL
INCH(BASE) MM(REF)
A
0.112 (MAX)
2.845 (MAX)
A1 0.004(MIN) 0.102(MIN)
A2
0.098
0.005 2.489
0.127
b 0.016
(TYP)
0.406(TYP)
c 0.010
(TYP)
0.254(TYP)
D
0.713
0.005 18.110
0.127
E
0.331
0.005 8.407
0.127
E1
0.465
0.012 11.811
0.305
e 0.050
(TYP)
1.270(TYP)
L
0.0404
0.008 1.0255
0.203
L1
0.067
0.008 1.702
0.203
S
0.047 (MAX)
1.194 (MAX)
y 0.003(MAX)
0.076(MAX)
0
o
10
o
0
o
10
o
UTRON TECHNOLOGY INC. P80060
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
9
UTRON
UT62L64C
Rev. 1.3
8K X 8 BIT LOW POWER CMOS SRAM
ORDERING INFORMATION
Commerical temperature
PART NO.
ACCESS TIME(ns)
STANDBY CURRENT
(
A)
(TYP.)
PACKAGE
UT62L64CPC-35
35
1.5mA
28 PIN PDIP
UT62L64CPC-35L 35
1A
28 PIN PDIP
UT62L64CPC-35LL 35
0.5A
28 PIN PDIP
UT62L64CPC-70
70
1.5mA
28 PIN PDIP
UT62L64CPC-70L 70
1A
28 PIN PDIP
UT62L64CPC-70LL 70
0.5A
28 PIN PDIP
UT62L64CSC-35
35
1.5mA
28 PIN SOP
UT62L64CSC-35L 35
1A
28 PIN SOP
UT62L64CSC-35LL 35
0.5A
28 PIN SOP
UT62L64CSC-70
70
1.5mA
28 PIN SOP
UT62L64CSC-70L 70
1A
28 PIN SOP
UT62L64CSC-70LL 70
0.5A
28 PIN SOP
Extended temperature
PART NO.
ACCESS TIME(ns)
STANDBY CURRENT
(
A)
(TYP.)
PACKAGE
UT62L64CPC-35E
35
1.5mA
28 PIN PDIP
UT62L64CPC-35LE 35
1A
28 PIN PDIP
UT62L64CPC-35LLE 35
0.5A
28 PIN PDIP
UT62L64CPC-70E
70
1.5mA
28 PIN PDIP
UT62L64CPC-70LE 70
1A
28 PIN PDIP
UT62L64CPC-70LLE 70
0.5A
28 PIN PDIP
UT62L64CSC-35E
35
1.5mA
28 PIN SOP
UT62L64CSC-35LE 35
1A
28 PIN SOP
UT62L64CSC-35LLE 35
0.5A
28 PIN SOP
UT62L64CSC-70E
70
1.5mA
28 PIN SOP
UT62L64CSC-70LE 70
1A
28 PIN SOP
UT62L64CSC-70LLE 70
0.5A
28 PIN SOP
UTRON TECHNOLOGY INC. P80060
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
10
UTRON
UT62L64C
Rev. 1.3
8K X 8 BIT LOW POWER CMOS SRAM
ORDERING INFORMATION (for lead free product)
Commerical temperature
PART NO.
ACCESS TIME(ns)
STANDBY CURRENT
(
A)
(TYP.)
PACKAGE
UT62L64CPCL-35
35
1.5mA
28 PIN PDIP
UT62L64CPCL-35L 35
1A
28 PIN PDIP
UT62L64CPCL-35LL 35
0.5A
28 PIN PDIP
UT62L64CPCL-70
70
1.5mA
28 PIN PDIP
UT62L64CPCL-70L 70
1A
28 PIN PDIP
UT62L64CPCL-70LL 70
0.5A
28 PIN PDIP
UT62L64CSCL-35
35
1.5mA
28 PIN SOP
UT62L64CSCL-35L 35
1A
28 PIN SOP
UT62L64CSCL-35LL 35
0.5A
28 PIN SOP
UT62L64CSCL-70
70
1.5mA
28 PIN SOP
UT62L64CSCL-70L 70
1A
28 PIN SOP
UT62L64CSCL-70LL 70
0.5A
28 PIN SOP
Extended temperature
PART NO.
ACCESS TIME(ns)
STANDBY CURRENT
(
A)
(TYP.)
PACKAGE
UT62L64CPCL-35E
35
1.5mA
28 PIN PDIP
UT62L64CPCL-35LE 35
1A
28 PIN PDIP
UT62L64CPCL-35LLE 35
0.5A
28 PIN PDIP
UT62L64CPCL-70E
70
1.5mA
28 PIN PDIP
UT62L64CPCL-70LE 70
1A
28 PIN PDIP
UT62L64CPCL-70LLE 70
0.5A
28 PIN PDIP
UT62L64CSCL-35E
35
1.5mA
28 PIN SOP
UT62L64CSCL-35LE 35
1A
28 PIN SOP
UT62L64CSCL-35LLE 35
0.5A
28 PIN SOP
UT62L64CSCL-70E
70
1.5mA
28 PIN SOP
UT62L64CSCL-70LE 70
1A
28 PIN SOP
UT62L64CSCL-70LLE 70
0.5A
28 PIN SOP
UTRON TECHNOLOGY INC. P80060
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
11
UTRON
UT62L64C
Rev. 1.3
8K X 8 BIT LOW POWER CMOS SRAM
THIS PAGE IS LEFT BLANK INTENTIONALLY.
UTRON TECHNOLOGY INC. P80060
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
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