UTRON
UT62W1024
Rev. 1.1
128K X 8 BIT WIDE RANGE LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80056
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
REVISION HISTORY
REVISION DESCRIPTION
DATE
REV. 0.9
Original.
Mar.15. 2001
REV. 1.0 1. The symbols CE1# ,OE# & WE# are revised as CE , OE &
WE
.
2. I
cc1
is
revise as I
cc
.
3. I
cc2
is
revise as I
cc1
.
Jul. 06. 2001
REV. 1.1 Add order information for lead free product
May. 16. 2003
UTRON
UT62W1024
Rev. 1.1
128K X 8 BIT WIDE RANGE LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80056
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
FEATURES
Access time : 35/55/70ns (max.)
Low power consumption :
Operating : 60/50/40 mA (typical)
Standby : 10
A (typical) L-version
1
A (typical) LL-version
Wide range power supply : 2.7V to 5.5V
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 32-pin 600 mil PDIP
32-pin 450 mil SOP
32-pin 8x20mm TSOP-1
32-pin 8x13.4mm STSOP
FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
1024 X 1024
MEMORY
ARRAY
COLUMN I/O
OE
W
E
A0-A16
Vcc
Vss
I/O1-I/O8
CE
CE2
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A16
Address Inputs
I/O1 - I/O8
Data Inputs/Outputs
CE ,CE2
Chip enable 1,2 Inputs
WE
Write Enable Input
OE
Output Enable Input
V
CC
Power
Supply
V
SS
Ground
NC No
Connection
GENERAL DESCRIPTION
The UT62W1024 is a 1,048,576-bit low power
CMOS static random access memory organized as
131,072 words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.
The UT62W1024 is designed for low power
application. It is particularly well suited for battery
back-up nonvolatile memory application.
The UT62W1024 operates from a wide range of
2.7V~ 5.5V power supply and all inputs and outputs
are fully TTL compatible.
PIN CONFIGURATION
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
CE2
A8
A9
A11
A10
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
UT62
W10
2
4
PDIP / SOP
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
CE
WE
OE
A13
A14
NC
A16
Vcc
A15
29
30
31
32
TSOP-I/STSOP
I/O4
A11
A9
A8
A13
I/O3
A10
A14
A12
A7
A6
A5
Vcc
I/O8
I/O7
I/O6
I/O5
Vss
I/O2
I/O1
A0
A1
A2
A4
A3
UT62W1024
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
WE
OE
CE
CE2
NC
A15
A16
32
31
30
29
UTRON
UT62W1024
Rev. 1.1
128K X 8 BIT WIDE RANGE LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80056
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
SYMBOL
RATING
UNIT
Terminal Voltage with Respect to Vss
V
TERM
-0.5 to +4.6
V
Operating Temperature
T
A
0 to +70
Storage Temperature
T
STG
-65 to +150
Power Dissipation
P
D
1
W
DC Output Current
I
OUT
50
mA
Soldering Temperature (under 10 sec)
T
solder
260
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
CE
CE2
OE
WE
I/O OPERATION
SUPPLY CURRENT
Standby
H
X
X
X
High - Z
I
SB
,
I
SB1
Standby
X
L
X
X
High -Z
I
SB
,
I
SB1
Output Disable
L
H
H
H
High - Z
I
CC
Read
L
H
L
H
D
OUT
I
CC
Write
L
H
X
L
D
IN
I
CC
Note: H = V
IH
, L=V
IL
, X = Don't care.
DC ELECTRICAL CHARACTERISTICS (
)
(V
CC
= 2.7V~3.6V, Vss=0V, T
A
= 0
to 70
)
PARAMETER
SYMBOL TEST CONDITION
MIN.
TYP.
MAX.
UNIT
Input High Voltage
V
IH
*1
2.0 -
V
CC
+0.5 V
Input Low Voltage
V
IL
*2
- 0.5
-
0.6
V
Input Leakage Current
I
IL
V
SS
V
IN
V
CC
- 1
-
1
A
Output Leakage Current
I
OL
V
SS
V
I/O
V
CC
CE =V
IH
or CE2=V
IL
or
OE
=V
IH
or
WE
=V
IL
- 1
-
1
A
Output High Voltage
V
OH
I
OH
= -1mA
2.2
-
-
V
Output Low Voltage
V
OL
I
OL
= 4mA
-
-
0.4
V
-35 - 40 60 mA
-55 - 35 50 mA
I
CC
Cycle time =Min. 100% Duty,
CE =V
IL
, CE2 = V
IH
,
I
I/O
= 0mA
-70 - 30 40 mA
Average Operating
Power Supply Courrent
I
CC1
Cycle time = 1s, 100% Duty,
CE
0.2V,CE2
V
CC
-0.2V,
C
L
=50PF
- - 5 mA
I
SB
CE =V
IH
or CE2 = V
IL
- - 1.0
mA
100
- L
-
2.5
20
*4
A
40
Standby Power
Supply Current
I
SB1
CE
V
CC
-0.2V or
CE2
0.2V
-
LL
- 0.5
10
*4
A
Notes:
1. Overshoot : Vcc+2.0v for pulse width less than 10ns.
2. Undershoot : Vss-2.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
4. Those parameters are for reference only under 50
UTRON
UT62W1024
Rev. 1.1
128K X 8 BIT WIDE RANGE LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80056
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
DC ELECTRICAL CHARACTERISTICS (
)
(V
CC
= 4.5V~5.5V, Vss=0V, TA = 0
to 70
)
PARAMETER
SYMBOL TEST CONDITION
MIN.
TYP.
MAX.
UNIT
Input High Voltage
V
IH
*1
2.2 -
V
CC
+0.5 V
Input Low Voltage
V
IL
*2
- 0.5
-
0.8
V
Input Leakage Current
I
IL
V
SS
V
IN
V
CC
- 1
-
1
A
Output Leakage Current
I
OL
V
SS
V
I/O
V
CC
CE =V
IH
or CE2=V
IL
or
OE
=V
IH
or
WE
=V
IL
- 1
-
1
A
Output High Voltage
V
OH
I
OH
=-1mA
2.4
-
-
V
Output Low Voltage
V
OL
I
OL
= 4mA
-
-
0.4
V
-35 - 60 100 mA
-55 - 50 85 mA
I
CC
Cycle time =Min. 100% Duty,
CE =V
IL
, CE2 = V
IH
,
C
L
=100PF
-70 - -40 70 mA
Average Operating
Power Supply Courrent
I
CC1
Cycle time = 1s, 100% Duty,
CE
0.2V,CE2
V
CC
-0.2V,
I
I/O
= 0mA
- - 5 mA
I
SB
CE =V
IH
or CE2 = V
IL
- - 1.0
mA
100
- L
-
2.5
20
*3
A
40
Standby Power
Supply Current
I
SB1
CE
V
CC
-0.2V or
CE2
0.2V
-
LL
- 0.5
10
*3
A
*1. V
IH
(max)=Vcc+3.0v for pulse width less than 10ns.
*2. V
IL
(min)=Vss-3.0v for pulse width less than 10ns.
*3. Those parameters are for reference only under 50
UTRON
UT62W1024
Rev. 1.1
128K X 8 BIT WIDE RANGE LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80056
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
CAPACITANCE (T
A
=25
, f=1.0MHz)
PARAMETER
SYMBOL MIN.
MAX.
UNIT
Input Capacitance
C
IN
-
8
pF
Input/Output Capacitance
C
I/O
-
10
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0V to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Reference Levels
1.5V
Output Load
C
L
=100pF, I
OH
/I
OL
=-1mA/4mA(V
CC
=5V)
C
L
=50pF, I
OH
/I
OL
=-1mA/2mA(V
CC
=3.3V)
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V~5.5V, V
SS
=0V , T
A
= 0
to 70
)
(1) READ CYCLE
PARAMETER
SYMBOL
UT62W1024-35 UT62W1024-55 UT62W1024-70
UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time
t
RC
35 - 55 - 70 - ns
Address Access Time
t
AA
- 35 - 55 - 70 ns
Chip Enable Access Time
t
ACE
- 35 - 55 - 70 ns
Output Enable Access Time
t
OE
- 25 - 30 - 35 ns
Chip Enable to Output in Low-Z
t
CLZ
*
10 - 10 - 10 - ns
Output Enable to Output in Low-Z t
OLZ
*
5 - 5 - 5 - ns
Chip Disable to Output in High-Z
t
CHZ
*
- 25 - 30 - 35 ns
Output Disable to Output in High-Z t
OHZ
*
- 25 - 30 - 35 ns
Output Hold from Address Change t
OH
5 - 5 - 5 - ns
(2) WRITE CYCLE
PARAMETER
SYMBOL
UT62W1024-35 UT62W1024-55 UT62W1024-70
UNIT
MIN.
MAX. MIN. MAX. MIN. MAX.
Write Cycle Time
t
WC
35 - 55 - 70 -
ns
Address Valid to End of Write
t
AW
30 - 50 - 60 -
ns
Chip Enable to End of Write
t
CW
30 - 50 - 60 -
ns
Address Set-up Time
t
AS
0
-
0
-
0
-
ns
Write Pulse Width
t
WP
25 - 40 - 45 -
ns
Write Recovery Time
t
WR
0
-
0
-
0
-
ns
Data to Write Time Overlap
t
DW
20 - 25 - 30 -
ns
Data Hold from End of Write-Time t
DH
0
-
0
-
0
-
ns
Output Active from End of Write
t
OW
*
5
-
5
-
5
-
ns
Write to Output in High-Z
t
WHZ
*
- 15 - 20 - 25
ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON
UT62W1024
Rev. 1.1
128K X 8 BIT WIDE RANGE LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80056
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
6
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
(1,2)
t
RC
t
AA
Data Valid
Address
Dout
t
OH
t
OH
Previous data valid
READ CYCLE 2
(
CE
and
CE2
and
OE
Controlled)
(1,3,4,5)
t
RC
t
AA
t
ACE
t
OE
t
OHZ
t
CLZ
t
OH
t
OLZ
High-Z
Data Valid
High-Z
t
CHZ
Address
CE2
Dout
CE
OE
Notes :
1.
WE
is high for read cycle.
2.Device is continuously selected OE =low, CE =low
,
CE2=high
.
3.Address must be valid prior to or coincident with CE =low
,
CE2=high; otherwise t
AA
is the limiting parameter.
4.t
CLZ
, t
OLZ
, t
CHZ
and t
OHZ
are specified with C
L
=5pF. Transition is measured
500mV from steady state.
5.At any given temperature and voltage condition, t
CHZ
is less than t
CLZ
, t
OHZ
is less than t
OLZ
.
UTRON
UT62W1024
Rev. 1.1
128K X 8 BIT WIDE RANGE LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80056
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
7
WRITE CYCLE 1
(
WE
Controlled)
(1,2,3,5,6)
t
WC
t
AW
t
CW
t
AS
t
WP
t
WHZ
t
OW
t
WR
High-Z
(4)
(4)
Address
CE2
CE
WE
Dout
Din
Data Valid
t
DW
t
DH
WRITE CYCLE 2
(
CE
and CE2
Controlled)
(1,2,5,6)
t
W C
t
A W
t
C W
t
A S
t
W R
t
W P
t
W H Z
t
D W
t
D H
Data Valid
High-Z
(4)
Address
CE2
CE
W E
Dout
Din
UTRON
UT62W1024
Rev. 1.1
128K X 8 BIT WIDE RANGE LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80056
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
8
Notes :
1.
WE
, CE must be high or CE2 must be low during all address transitions.
2.A write occurs during the overlap of a low CE , high CE2, low
WE
.
3. During a
WE
controlled write cycle with OE low, t
WP
must be greater than t
WHZ
+t
DW
to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CE low transition and CE2 high transition occurs simultaneously with or after
WE
low transition, the outputs remain in a high
impedance state.
6.t
OW
and t
WHZ
are specified with C
L
= 5pF. Transition is measured
500mV from steady state.
DATA RETENTION CHARACTERISTICS (T
A
= 0
to 70
)
PARAMETER
SYMBOL TEST CONDITION
MIN.
TYP.
MAX.
UNIT
Vcc for Data Retention
V
DR
CE
V
CC
-0.2V or
CE2
0.2V
2.0
-
-
V
80
Data Retention Current
I
DR
Vcc=3V
- L -
2
20*
A
20
CE
V
CC
-0.2V or
CE2
0.2V
- LL -
0.5
10*
A
Chip Disable to Data
t
CDR
See Data Retention
0
-
-
ns
Retention Time
Waveforms (below)
Recovery Time
t
R
t
RC
*
-
-
ns
t
RC
* = Read Cycle Time
*Those parameters are for reference only under 50
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1)
(
CE
controlled)
VDR
2V
CE
V
CC
-0.2V
V
cc(min.)
V
cc(min.)
V
IH
V
IH
V
CC
t
R
t
CDR
CE
Low Vcc Data Retention Waveform (2)
(CE2 controlled)
VDR
2V
V
CC(min.)
V
CC
t
R
t
CDR
CE2
0.2V
V
IL
CE2
V
CC(min.)
V
IL
UTRON
UT62W1024
Rev. 1.1
128K X 8 BIT WIDE RANGE LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80056
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
9
PACKAGE OUTLINE DIMENSION
32 pin 600 mil PDIP Package Outline Dimension
UNIT
SYMBOL
INCH(BASE) MM(REF)
A1
0.010 (MIN)
0.254 (MIN)
A2
0.150
0.005 3.810
0.127
B
0.018
0.005 0.457
0.127
B1
0.050
0.005 1.270
0.127
c
0.010
0.004 0.254
0.102
D
1.650
0.005 41.910
0.127
E
0.600
0.010 15.240
0.254
E1
0.544
0.004 13.818
0.102
e
0.100 (TYP)
2.540 (TYP)
eB
0.640
0.020 16.256
0.508
L
0.130
0.010 3.302
0.254
S
0.075
0.010 1.905
0.254
Q1
0.070
0.005 1.778
0.127
Note:
1. D/E1/S DIMENSION DO NOT INCLUDE MOLD FLASH.
UTRON
UT62W1024
Rev. 1.1
128K X 8 BIT WIDE RANGE LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80056
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
10
32 pin 450mil SOP Package Outline Dimension
UNIT
SYMBOL
INCH(BASE) MM(REF)
A
0.118 (MAX)
2.997 (MAX)
A1 0.004(MIN)
0.102(MIN)
A2 0.111(MAX)
2.82(MAX)
b 0.016(TYP)
0.406(TYP)
c 0.008(TYP)
0.203(TYP)
D 0.817(MAX)
20.75(MAX)
E
0.445
0.005 11.303
0.127
E1
0.555
0.012 14.097
0.305
e 0.050(TYP)
1.270(TYP)
L
0.0347
0.008 0.881
0.203
L1
0.055
0.008 1.397
0.203
S 0.026(MAX)
0.066
(MAX)
y
0.004(MAX) 0.101(MAX)
0
o
-10
o
0
o
-10
o
UTRON
UT62W1024
Rev. 1.1
128K X 8 BIT WIDE RANGE LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80056
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
11
32 pin TSOP-I Package Outline Dimension
UNIT
SYMBOL
INCH(BASE) MM(REF)
A
0.047 (MAX)
1.20 (MAX)
A1
0.004
0.002 0.10
0.05
A2
0.039
0.002 1.00
0.05
b
0.008 + 0.002
- 0.001
0.20 + 0.05
-0.03
c
0.005 (TYP)
0.127 (TYP)
D
0.724
0.004 18.40
0.10
E
0.315
0.004 8.00
0.10
e
0.020 (TYP)
0.50 (TYP)
HD
0.787
0.008 20.00
0.20
L
0.0197
0.004 0.50
0.10
L1
0.0315
0.004 0.08
0.10
y
0.003 (MAX)
0.076 (MAX)
0
o
5
o
0
o
5
o
UTRON
UT62W1024
Rev. 1.1
128K X 8 BIT WIDE RANGE LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80056
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
12
32 pin 8mm x 13.4mm STSOP Package Outline Dimension
1
16
17
32
cL
HD
D
"A"
E
e
12
(2x)
12
(2x)
Seating Plane
y
32
17
16
1
c
A2
A1
L
A
0.
25
4
0
GAUGE PLANE
12
(2X)
12
(2X)
SEATING PLANE
"A" DATAIL VIEW
L1
b
UNIT
SYMBOL
INCH(BASE) MM(REF)
A
0.049 (MAX)
1.25 (MAX)
A1
0.005
0.002 0.130
0.05
A2
0.039
0.002 1.00
0.05
b
0.008
0.01 0.20
0.025
c
0.005 (TYP)
0.127 (TYP)
D
0.465
0.004 11.80
0.10
E
0.315
0.004 8.00
0.10
e
0.020 (TYP)
0.50 (TYP)
HD
0.528
0.008 13.40
0.20.
L
0.0197
0.004 0.50
0.10
L1
0.0315
0.004 0.8
0.10
y
0.003 (MAX)
0.076 (MAX)
0
o
5
o
0
o
5
o
UTRON
UT62W1024
Rev. 1.1
128K X 8 BIT WIDE RANGE LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80056
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
13
ORDERING INFORMATION
PART NO.
ACCESS TIME
(ns)
STANDBY CURRENT
(
A)
PACKAGE
UT62W1024PC-35L
35
500
32 PIN PDIP
UT62W1024PC-35LL
35
50
32 PIN PDIP
UT62W1024SC-35L
35
500
32 PIN SOP
UT62W1024SC-35LL
35
50
32 PIN SOP
UT62W1024LC-35L
35
500
32 PIN TSOP-I
UT62W1024LC-35LL
35
50
32 PIN TSOP-I
UT62W1024LS-35L
35
500
32 PIN STSOP
UT62W1024LS-35LL
35
50
32 PIN STSOP
UT62W1024PC-55L
55
500
32 PIN PDIP
UT62W1024PC-55LL
55
50
32 PIN PDIP
UT62W1024SC-55L
55
500
32 PIN SOP
UT62W1024SC-55LL
55
50
32 PIN SOP
UT62W1024LC-55L
55
500
32 PIN TSOP-I
UT62W1024LC-55LL
55
50
32 PIN TSOP-I
UT62W1024LS-55L
55
500
32 PIN STSOP
UT62W1024LS-55LL
55
50
32 PIN STSOP
UT62W1024PC-70L
70
500
32 PIN PDIP
UT62W1024PC-70LL
70
50
32 PIN PDIP
UT62W1024SC-70L
70
500
32 PIN SOP
UT62W1024SC-70LL
70
50
32 PIN SOP
UT62W1024LC-70L
70
500
32 PIN TSOP-I
UT62W1024LC-70LL
70
50
32 PIN TSOP-I
UT62W1024LS-70L
70
500
32 PIN STSOP
UT62W1024LS-70LL
70
50
32 PIN STSOP
UTRON
UT62W1024
Rev. 1.1
128K X 8 BIT WIDE RANGE LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80056
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
14
ORDERING INFORMATION (for lead free product)
PART NO.
ACCESS TIME
(ns)
STANDBY CURRENT
(
A)
PACKAGE
UT62W1024PCL-35L
35
500
32 PIN PDIP
UT62W1024PCL-35LL
35
50
32 PIN PDIP
UT62W1024SCL-35L
35
500
32 PIN SOP
UT62W1024SCL-35LL
35
50
32 PIN SOP
UT62W1024LCL-35L
35
500
32 PIN TSOP-I
UT62W1024LCL-35LL
35
50
32 PIN TSOP-I
UT62W1024LSL-35L
35
500
32 PIN STSOP
UT62W1024LSL-35LL
35
50
32 PIN STSOP
UT62W1024PCL-55L
55
500
32 PIN PDIP
UT62W1024PCL-55LL
55
50
32 PIN PDIP
UT62W1024SCL-55L
55
500
32 PIN SOP
UT62W1024SCL-55LL
55
50
32 PIN SOP
UT62W1024LCL-55L
55
500
32 PIN TSOP-I
UT62W1024LCL-55LL
55
50
32 PIN TSOP-I
UT62W1024LSL-55L
55
500
32 PIN STSOP
UT62W1024LSL-55LL
55
50
32 PIN STSOP
UT62W1024PCL-70L
70
500
32 PIN PDIP
UT62W1024PCL-70LL
70
50
32 PIN PDIP
UT62W1024SCL-70L
70
500
32 PIN SOP
UT62W1024SCL-70LL
70
50
32 PIN SOP
UT62W1024LCL-70L
70
500
32 PIN TSOP-I
UT62W1024LCL-70LL
70
50
32 PIN TSOP-I
UT62W1024LSL-70L
70
500
32 PIN STSOP
UT62W1024LSL-70LL
70
50
32 PIN STSOP
UTRON
UT62W1024
Rev. 1.1
128K X 8 BIT WIDE RANGE LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80056
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
15
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