UTRON
UT62W256C
Rev. 1.1
32K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80069
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
REVISION HISTORY
REVISION DESCRIPTION Draft
Date
Rev. 1.0
Original.
Aug.13. 2001
Rev. 1.1
1.Add Extended temperature : -20
~85
2.Add order information for lead free product
Apr. 21. 2003
UTRON
UT62W256C
Rev. 1.1
32K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80069
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
FEATURES
Fast access time : 35/70ns
Low power consumption:
Operation : 40/20 mA (max.) (V
CC
3.6
V)
50/40 mA (max.) (V
CC
5.5
V)
Standby : -L / -LL version
1 / 0.5uA (typical) V
CC
=2.7~3.6V
2 / 1uA (typical) V
CC
=4.5~5.5V
Wide Range power supply: 2.7V~5.5V
Operating temperature :
Commercial temperature : 0
~70
Extended temperature : -20
~85
All inputs and outputs are TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 1.5V (min.)
Package : 28-pin 600 mil PDIP
28-pin 330 mil SOP
28-pin 8x13.4mm STSOP
FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
32K
8
MEMORY
ARRAY
COLUMN I/O
OE
WE
A0-A14
Vcc
Vss
I/O1-I/O8
CE
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A14
Address Inputs
I/O1 - I/O8
Data Inputs/Outputs
CE
Chip Enable Input
WE
Write Enable Input
OE
Output Enable Input
V
CC
Power
Supply
V
SS
Ground
GENERAL DESCRIPTION
The UT62W256C is a 262,144-bit low power CMOS
static random access memory organized as 32,768
words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology. its
standby current is stable within the range of operating
temperature.
The UT62W256C is designed for low power
application. It is particularly well suited for battery
back-up nonvolatile memory application.
The UT62W256C operates with wide range power
supply and all inputs and outputs are fully TTL
compatible
PIN CONFIGURATION
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
Vcc
A8
A9
A11
A10
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
UT62W256C
PDIP/SOP
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
CE
WE
OE
A13
A14
I/O4
A11
A9
A8
A13
I/O3
A10
A14
A12
A7
A6
A5
Vcc
I/O8
I/O7
I/O6
I/O5
Vss
I/O2
I/O1
A0
A1
A2
A4
A3
UT62W256C
STSOP
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
WE
OE
CE
UTRON
UT62W256C
Rev. 1.1
32K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80069
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
ABSOLUTE MAXIMUM RATINGS*
PARAMETER SYMBOL
RATING
UNIT
Terminal Voltage with Respect to V
SS
V
TERM
-0.5 to 7.0
V
Commercial T
A
0 to 70
Operation Temperature
Extended T
A
-20 to 85
Storage Temperature
T
STG
-65 to 150
Power Dissipation
P
D
1
W
DC Output Current
I
OUT
50
mA
Soldering Temperature (under 10 sec)
Tsolder
260
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
CE
OE
WE
I/O OPERATION
SUPPLY CURRENT
Standby
H
X
X
High - Z
I
SB
, I
SB1
Output Disable
L
H
H
High - Z
I
CC
,I
CC1
,I
CC2
Read L
L
H
D
OUT
I
CC
,I
CC1
,I
CC2
Write L
X
L
D
IN
I
CC
,I
CC1
,I
CC2
Note: H = V
IH
, L=V
IL
, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
(T
A
= 0
to 70
/ -20
to 85
(E))
PARAMETER
SYMBOL
TEST CONDITION
MIN. TYP. MAX. MIN. TYP. MAX.
UNIT
Power Supply Voltage
V
CC
2.7~3.6
4.5~5.5
V
Input High Voltage
V
IH
1
2.0 -
V
CC
+0.5
2.2 -
V
CC
+0.5
V
Input Low Voltage
V
IL
2
- 0.5
-
0.6
- 0.5
-
0.8
V
Input Leakage Current
I
LI
V
SS
V
IN
V
CC
- 1
-
1
- 1
-
1
A
Output Leakage
Current
I
LO
V
SS
V
I/O
V
CC
,
CE
=V
IH
or
OE
= V
IH
or
WE
= V
IL
- 1
-
1
- 1
-
1
A
Output High Voltage
V
OH
I
OH
= - 1mA
2.2
-
-
2.4
-
-
V
Output Low Voltage
V
OL
I
OL
=
4mA
- - 0.4 - - 0.4 V
-
35
- - 40 - 40 50 mA
I
CC
CE
= V
IL
,I
I/O
=
0mA ,Cycle=Min. - 70
- - 20 - 30 40 mA
I
CC
1
Cycle=1s
CE
=0.2V;
I
I/O
= 0mA other pins at
0.2V or V
CC
-0.2V
- - 6 - - 10 mA
Operation Power
Supply Current
I
CC
2
Cycle=500ns
CE
=0.2V
; I
I/O
= 0mA other pins
at 0.2V or V
CC
-0.2V
- - 12 - - 20 mA
I
SB
CE
=V
IH
- 3 - 3 mA
-L - 1 40 - 2 100 A
Standby Power Supply
Current
I
SB1
CE
V
CC
-0.2V
-LL - 0.5 20 - 1 50 A
Notes:
1. Overshoot : Vcc+2.0v for pulse width less than 10ns.
2. Undershoot : Vss-2.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON
UT62W256C
Rev. 1.1
32K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80069
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
CAPACITANCE (T
A
=25
, f=1.0MHz)
PARAMETER
SYMBOL
MIN.
MAX
UNIT
Input Capacitance
C
IN
-
8 pF
Input/Output Capacitance
C
I/O
-
10 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0V to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Reference Levels
1.5V
Output Load
C
L
= 100Pf+1TTL, I
OH
/I
OL
= -1mA/4mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V~5.5V , T
A
= 0
to 70
/ -20
to 85
(E))
(1) READ CYCLE
UT62W256C-35 UT62W256C-70
PARAMETER
SYMBOL
MIN. MAX. MIN. MAX.
UNIT
Read Cycle Time
t
RC
35
-
70
-
ns
Address Access Time
t
AA
-
35
-
70
ns
Chip Enable Access Time
t
ACE
-
35
-
70
ns
Output Enable Access Time
t
OE
-
25
-
35
ns
Chip Enable to Output in Low Z
t
CLZ*
10
-
10
- ns
Output Enable to Output in Low Z
t
OLZ*
5
-
5
- ns
Chip Disable to Output in High Z
t
CHZ*
-
25
-
35
ns
Output Disable to Output in High Z
t
OHZ*
-
25
-
35
ns
Output Hold from Address Change
t
OH
5
-
5
-
ns
(2) WRITE CYCLE
UT62W256C-35 UT62W256C-70
PARAMETER SYMBOL
MIN. MAX. MIN. MAX.
UNIT
Write Cycle Time
t
WC
35
-
70
- ns
Address Valid to End of Write
t
AW
30
-
60
- ns
Chip Enable to End of Write
t
CW
30
-
60
- ns
Address Set-up Time
t
AS
0
-
0
-
ns
Write Pulse Width
t
WP
25
-
50
- ns
Write Recovery Time
t
WR
0
-
0
- ns
Data to Write Time Overlap
t
DW
20
-
30
- ns
Data Hold from End of Write Time
t
DH
0
-
0
-
ns
Output Active from End of Write
t
OW*
5
-
5
- ns
Write to Output in High Z
t
WHZ*
-
15
-
25 ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON
UT62W256C
Rev. 1.1
32K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80069
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
(1,2)
t
RC
t
AA
Data Valid
Address
Dout
t
OH
t
OH
Previous data valid
READ CYCLE 2
(
CE
and
OE
Controlled)
(1,3,4,5)
t
RC
t
AA
t
ACE
t
OE
t
OHZ
t
CLZ
t
OH
t
OLZ
High-Z
Data Valid
High-Z
t
CHZ
Address
Dout
CE
OE
Notes :
1.
WE
is high for read cycle.
2.Device is continuously selected OE =low, CE =low
.
3.Address must be valid prior to or coincident with CE =low
,
; otherwise t
AA
is the limiting parameter.
4.t
CLZ
, t
OLZ
, t
CHZ
and t
OHZ
are specified with C
L
=5pF. Transition is measured
500mV from steady state.
5.At any given temperature and voltage condition, t
CHZ
is less than t
CLZ
, t
OHZ
is less than t
OLZ
.
UTRON
UT62W256C
Rev. 1.1
32K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80069
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
6
WRITE CYCLE 1
(
WE
Controlled)
(1,2,3,5,6)
t
WC
t
AW
t
CW
t
AS
t
WP
t
WHZ
t
OW
t
WR
High-Z
(4)
(4)
Address
CE
WE
Dout
Din
Data Valid
t
DW
t
DH
WRITE CYCLE 2
(
CE
Controlled)
(1,2,5,6)
t
W C
t
A W
t
C W
t
A S
t
W R
t
W P
t
W H Z
t
D W
t
D H
Data Valid
High-Z
(4)
Address
CE
W E
Dout
Din
UTRON
UT62W256C
Rev. 1.1
32K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80069
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
7
Notes :
1.
WE
, CE must be high during all address transitions.
2.A write occurs during the overlap of a low CE , low
WE
.
3. During a
WE
controlled write cycle with OE low, t
WP
must be greater than t
WHZ
+t
DW
to allow the drivers to turn off and data to be placed
on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CE low transition occurs simultaneously with or after
WE
low transition, the outputs remain in a high impedance state.
6.t
OW
and t
WHZ
are specified with C
L
= 5pF. Transition is measured
500mV from steady state.
DATA RETENTION CHARACTERISTICS
(T
A
= 0
to 70
/ -20
to 85
(E))
PARAMETER SYMBOL
TEST
CONDITION
MIN.
TYP.
MAX.
UNIT
Vcc for Data Retention
V
DR
CE
V
CC
-0.2V
1.5 - 5.5 V
Vcc=1.5V
- L
-
1
20
A
Data Retention Current
I
DR
CE
V
CC
-0.2V
- LL
-
0.5
10
A
Chip Disable to Data
t
CDR
See Data Retention
0
-
-
ns
Retention Time
Waveforms
(below)
Recovery Time
t
R
t
RC*
- - ns
t
RC*
= Read Cycle Time
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform
(
CE
controlled)
V
DR
1.5V
CE
V
CC
-0.2V
V
cc(min.)
V
cc(min.)
V
IH
V
IH
V
CC
t
R
t
CDR
CE
UTRON
UT62W256C
Rev. 1.1
32K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80069
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
8
PACKAGE OUTLINE DIMENSION
28 pin 600 mil PDIP PACKAGE OUTLINE DIMENSION
UNIT
SYMBOL
INCH(BASE) MM(REF)
A1 0.010(MIN) 0.254(MIN)
A2
0.150
0.001 3.810
0.254
B
0.018
0.005 0.457
0.127
c
0.010
0.004 0.254
0.102
D
1.460
0.005 37.084
0.127
E
0.600
0.010 15.240
0.254
e 0.100
(TYP)
2.540(TYP)
eB
0.640
0.03 16.256
0.762
L
0.130
0.010 3.302
0.254
0
o
~15
o
0
o
~15
o
UTRON
UT62W256C
Rev. 1.1
32K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80069
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
9
28 pin 330 mil SOP PACKAGE OUTLINE DIMENSION
UNIT
SYMBOL
INCH(BASE) MM(REF)
A
0.112 (MAX)
2.845 (MAX)
A1 0.004(MIN) 0.102(MIN)
A2
0.098
0.005 2.489
0.127
b 0.016
(TYP)
0.406(TYP)
c 0.010
(TYP)
0.254(TYP)
D
0.713
0.005 18.110
0.127
E
0.331
0.005 8.407
0.127
E1
0.465
0.012 11.811
0.305
e 0.050
(TYP)
1.270(TYP)
L
0.0404
0.008 1.0255
0.203
L1
0.067
0.008 1.702
0.203
S
0.047 (MAX)
1.194 (MAX)
y 0.003(MAX)
0.076(MAX)
0
o
10
o
0
o
10
o
UTRON
UT62W256C
Rev. 1.1
32K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80069
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
10
28 pin 8x13.4mm STSOP PACKAGE OUTLINE DIMENSION
1
14
15
28
cL
HD
D
"A"
E
e
Seating Plane
y
28
15
14
1
c
A2
A1
A
0
SEATING PLANE
"A" DATAIL VIEW
L1
UNIT
SYMBOL
INCH(BASE) MM(REF)
A
0.047 (MAX)
1.20 (MAX)
A1 0.004
0.002 0.10
0.05
A2 0.039
0.002 1.00
0.05
D 0.465
0.004 11.800
0.100
E 0.315
0.004 8.000
0.100
e
0.022 (TYP)
0.55 (TYP)
HD 0.528
0.008 13.40
0.20.
L1 0.0315
0.004 0.80
0.10
y
0.003 (MAX)
0.076 (MAX)
0
o
5
o
0
o
5
o
UTRON
UT62W256C
Rev. 1.1
32K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80069
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
11
ORDERING INFORMATION
Commercial temperature :
PART NO.
ACCESS TIME (ns)
STANDBY CURRENT
(
A) max.
PACKAGE
UT62W256CPC-35L 35
100A
28PIN PDIP
UT62W256CPC-35LL 35
50A
28PIN PDIP
UT62W256CPC-70L 70
100A
28PIN PDIP
UT62W256CPC-70LL 70
50A
28PIN PDIP
UT62W256CSC-35L 35
100A
28PIN SOP
UT62W256CSC-35LL 35
50A
28PIN SOP
UT62W256CSC-70L 70
100A
28PIN SOP
UT62W256CSC-70LL 70
50A
28PIN SOP
UT62W256CLS-35L 35
100A
28PIN STSOP
UT62W256CLS-35LL 35
50A
28PIN STSOP
UT62W256CLS-70L 70
100A
28PIN STSOP
UT62W256CLS-70LL 70
50A
28PIN STSOP
Extended temperature :
PART NO.
ACCESS TIME (ns)
STANDBY CURRENT
(
A) max.
PACKAGE
UT62W256CPC-35LE 35
100A
28PIN PDIP
UT62W256CPC-35LLE 35
50A
28PIN PDIP
UT62W256CPC-70LE 70
100A
28PIN PDIP
UT62W256CPC-70LLE 70
50A
28PIN PDIP
UT62W256CSC-35LE 35
100A
28PIN SOP
UT62W256CSC-35LLE 35
50A
28PIN SOP
UT62W256CSC-70LE 70
100A
28PIN SOP
UT62W256CSC-70LLE 70
50A
28PIN SOP
UT62W256CLS-35LE 35
100A
28PIN STSOP
UT62W256CLS-35LLE 35
50A
28PIN STSOP
UT62W256CLS-70LE 70
100A
28PIN STSOP
UT62W256CLS-70LLE 70
50A
28PIN STSOP
UTRON
UT62W256C
Rev. 1.1
32K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80069
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
12
ORDERING INFORMATION
(for lead free product)
Commercial temperature :
PART NO.
ACCESS TIME (ns)
STANDBY CURRENT
(
A) max.
PACKAGE
UT62W256CPCL-35L 35
100A
28PIN PDIP
UT62W256CPCL-35LL 35
50A
28PIN PDIP
UT62W256CPCL-70L 70
100A
28PIN PDIP
UT62W256CPCL-70LL 70
50A
28PIN PDIP
UT62W256CSCL-35L 35
100A
28PIN SOP
UT62W256CSCL-35LL 35
50A
28PIN SOP
UT62W256CSCL-70L 70
100A
28PIN SOP
UT62W256CSCL-70LL 70
50A
28PIN SOP
UT62W256CLSL-35L 35
100A
28PIN STSOP
UT62W256CLSL-35LL 35
50A
28PIN STSOP
UT62W256CLSL-70L 70
100A
28PIN STSOP
UT62W256CLSL-70LL 70
50A
28PIN STSOP
Extended temperature :
PART NO.
ACCESS TIME (ns)
STANDBY CURRENT
(
A) max.
PACKAGE
UT62W256CPCL-35LE 35
100A
28PIN PDIP
UT62W256CPCL-35LLE 35
50A
28PIN PDIP
UT62W256CPCL-70LE 70
100A
28PIN PDIP
UT62W256CPCL-70LLE 70
50A
28PIN PDIP
UT62W256CSCL-35LE 35
100A
28PIN SOP
UT62W256CSCL-35LLE 35
50A
28PIN SOP
UT62W256CSCL-70LE 70
100A
28PIN SOP
UT62W256CSCL-70LLE 70
50A
28PIN SOP
UT62W256CLSL-35LE 35
100A
28PIN STSOP
UT62W256CLSL-35LLE 35
50A
28PIN STSOP
UT62W256CLSL-70LE 70
100A
28PIN STSOP
UT62W256CLSL-70LLE 70
50A
28PIN STSOP
UTRON
UT62W256C
Rev. 1.1
32K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80069
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
13
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