UTRON
UT62W64C
Rev. 1.0
8K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80096
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
REVISION HISTORY
REVISION DESCRIPTION Draft
date
Rev. 1.0
Original.
Apr. 08. 2003
UTRON
UT62W64C
Rev. 1.0
8 KX 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80096
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
FEATURES
Fast access time : 35/70ns
Low power consumption:
Operation : 40/20 mA (max.) (V
CC
3.6
V)
50/40 mA (max.) (V
CC
5.5
V)
Standby : -L / -LL version
1 / 0.5uA (typical) V
CC
=2.7~3.6V
2 / 1uA (typical) V
CC
=4.5~5.5V
Wide Range power supply: 2.7V~5.5V
Operating temperature :
Commercial : 0
~70
Extended : -20
~85
All inputs and outputs are TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 1.5V (min.)
Package : 28-pin 600mil PDIP
28-pin 330 mil SOP
FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
8K X 8
MEMORY
ARRAY
COLUMN I/O
OE
WE
A0-A12
Vcc
Vss
I/O1-I/O8
CE
CE2
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A12
Address Inputs
I/O1 - I/O8
Data Inputs/Outputs
CE ,CE2
Chip Enable Inputs
WE
Write Enable Input
OE
Output Enable Input
V
CC
Power
Supply
V
SS
Ground
NC No
connection
GENERAL DESCRIPTION
The UT62W64C is a 65,536-bit low power CMOS
static random access memory organized as 8,192
words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.
its standby current is stable within the range of
operating temperature.
The UT62W64C is designed for low power
application. It is particularly well suited for battery
back-up nonvolatile memory application.
The UT62W64C operates with wide range power
supply and all inputs and outputs are fully TTL
compatible
PIN CONFIGURATION
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
Vcc
A8
A9
A11
A10
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
UT6264C
PDIP/SOP
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
CE
WE
OE
CE2
NC
UTRON
UT62W64C
Rev. 1.0
8K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80096
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
ABSOLUTE MAXIMUM RATINGS*
PARAMETER SYMBOL
RATING
UNIT
Terminal Voltage with Respect to V
SS
V
TERM
-0.5 to 7.0
V
T
A
0 to 70
Operation Temperature
T
A
-20 to 85
Storage Temperature
T
STG
-65 to 150
Power Dissipation
P
D
1
W
DC Output Current
I
OUT
50
mA
Soldering Temperature (under 10 sec)
Tsolder
260
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
CE
CE2
OE
WE
I/O OPERATION
SUPPLY CURRENT
Standby
H
X
X
X
High - Z
I
SB,
I
SB1
Standby
X L X X
High
-
Z
I
SB,
I
SB1
Output Disable
L
H
H
H
High - Z
I
CC,
I
CC1,
I
CC2
Read
L H L H
D
OUT
I
CC,
I
CC1,
I
CC2
Write L
H
X
L D
IN
I
CC,
I
CC1,
I
CC2
Note: H = V
IH
, L=V
IL
, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
(T
A
= 0
to 70
/ -20
to 85
(E))
PARAMETER SYMBOL
TEST
CONDITION
MIN. TYP. MAX. MIN. TYP. MAX. UNIT
Power Supply Voltage
V
CC
2.7~3.6
4.5~5.5
V
Input High Voltage
V
IH
1
2.0 - V
CC
+0.5 2.2 - V
CC
+0.5 V
Input Low Voltage
V
IL
2
- 0.5
-
0.6
- 0.5
-
0.8
V
Input Leakage Current
I
LI
V
SS
V
IN
V
CC
- 1
-
1
- 1
-
1
A
Output Leakage
Current
I
LO
V
SS
V
I/O
V
CC
CE
= V
IH
or CE2= V
IL
or
OE
= V
IH
or
WE
=V
IL
- 1
-
1
- 1
-
1
A
Output High Voltage
V
OH
I
OH
= - 1mA
2.2
-
-
2.4
-
-
V
Output Low Voltage
V
OL
I
OL
=
4mA
- - 0.4 - - 0.4 V
-
35
- - 40 -
40 50
mA
I
CC
Cycle time=Min, I
I/O
= 0mA,
CE
= V
IL
,CE2= V
IH
-
70
- - 20 -
30 40
mA
I
CC1
TCycle =1us,
CE
=0.2V; I
I/O
=
0mA other pins at 0.2V or
Vcc-0.2V;
- - 6 - - 10 mA
Operation Power
Supply Current
I
CC2
Tcycle =500ns,
CE
=0.2V; I
I/O
=
0mA , other pins at 0.2V or
Vcc-0.2V
- - 12 - - 20
mA
I
SB
CE
= V
IH
or CE2= V
IL
other pins=V
IL
or V
IH
- 3 - 3 mA
-L
- 1 40 - 2 100 A
Standby Power
Supply Current
I
SB1
CE
V
CC
-0.2V or
CE2
0.2V , other pins
at 0.2V or Vcc-0.2V
-LL
- 0.5 20 - 1 50 A
Notes:
1. Overshoot : Vcc+2.0v for pulse width less than 10ns.
2. Undershoot : Vss-2.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON
UT62W64C
Rev. 1.0
8 KX 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80096
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
CAPACITANCE (T
A
=25
, f=1.0MHz)
PARAMETER
SYMBOL
MIN.
MAX
UNIT
Input Capacitance
C
IN
-
8 pF
Input/Output Capacitance
C
I/O
-
10 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0V to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Reference Levels
1.5V
Output Load
C
L
= 100pF+1TTL, I
OH
/I
OL
= -1mA/4mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V~5.5V , T
A
= 0
to 70
/ -20
to 85
(E))
(1) READ CYCLE
UT62W64C-35 UT62W64C-70
PARAMETER
SYMBOL
MIN. MAX. MIN. MAX.
UNIT
Read Cycle Time
t
RC
35
-
70
-
ns
Address Access Time
t
AA
-
35
-
70
ns
Chip Enable Access Time
t
ACE
-
35
-
70
ns
Output Enable Access Time
t
OE
-
25
-
35
ns
Chip Enable to Output in Low Z
t
CLZ*
10
-
10
- ns
Output Enable to Output in Low Z
t
OLZ*
5
-
5
-
ns
Chip Disable to Output in High Z
t
CHZ*
-
25
-
35
ns
Output Disable to Output in High Z
t
OHZ*
-
25
-
35
ns
Output Hold from Address Change
t
OH
5
-
5
-
ns
(2) WRITE CYCLE
UT62W64C-35 UT62W64C-70
PARAMETER SYMBOL
MIN. MAX. MIN. MAX.
UNIT
Write Cycle Time
t
WC
35
-
70
-
ns
Address Valid to End of Write
t
AW
30
-
60
-
ns
Chip Enable to End of Write
t
CW
30
-
60
-
ns
Address Set-up Time
t
AS
0 - 0 - ns
Write Pulse Width
t
WP
25
-
50
-
ns
Write Recovery Time
t
WR
0 - 0 - ns
Data to Write Time Overlap
t
DW
20
-
30
-
ns
Data Hold from End of Write Time
t
DH
0 - 0 - ns
Output Active from End of Write
t
OW*
5 - 5 - ns
Write to Output in High Z
t
WHZ*
-
15
-
25
ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON
UT62W64C
Rev. 1.0
8 KX 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80096
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
(1,2)
t
RC
t
AA
Data Valid
Address
Dout
t
OH
t
OH
Previous data valid
READ CYCLE 2
(
CE
and
CE2
and
OE
Controlled)
(1,3,4,5)
t
RC
t
AA
t
ACE
t
OE
t
OHZ
t
CLZ
t
OH
t
OLZ
High-Z
Data Valid
High-Z
t
CHZ
Address
CE2
Dout
CE
OE
Notes :
1.
WE
is high for read cycle.
2.Device is continuously selected OE =low, CE =low
,
CE2=high
.
3.Address must be valid prior to or coincident with CE =low
,
CE2=high; otherwise t
AA
is the limiting parameter.
4.t
CLZ
, t
OLZ
, t
CHZ
and t
OHZ
are specified with C
L
=5pF. Transition is measured
500mV from steady state.
5.At any given temperature and voltage condition, t
CHZ
is less than t
CLZ
, t
OHZ
is less than t
OLZ
.
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