UTRON
UT65L168(E)/UT65L168(I)
Rev. 1.1
512K X 16 BITS LOW POWER PSEUDO SRAM
UTRON TECHNOLOGY INC. P80094
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
REVISION HISTORY
REVISION DESCRIPTION
Draft
Date
Rev. 1.0
Original.
Apr. 15, 2003
Rev. 1.1
1. Delete Partial refresh function
2. Add Package : 48-pin 12mmX20mm TSOP-I
Aug. 06,2003
UTRON
UT65L168(E)/UT65L168(I)
Rev. 1.1
512K X 16 BITS LOW POWER PSEUDO SRAM
UTRON TECHNOLOGY INC. P80094
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
FEATURES
Fast access time : 60/70ns (max.)
Low operating power
Operating current : 20mA (typ)
Standby current : 50uA (typ)
Power supply voltage : 2.5V~3.3V
Operating temperature :
Extended(E) : -20 ~ 80
Industrial(I) : -40 ~ 85
Low power modes
Deep power Down : Isb < 10uA
Three state output and TTL compatible
Separated I/O power (Vccq) & Core Power (Vcc)
Page mode operation by 8 words
Data byte control :
LB
(I/O1~I/O8)
UB (I/O9~I/O16)
Package : 48-pin 6.0mm 8.0mm TFBGA
48-pin 12mmX20mm TSOP-I
FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
512K 16
MEMORY
ARRAY
COLUMN I/O
OE
WE
A0-A18
Vccq
Vss
I/O1-I/O8
Lower Byte
I/O9-I/O16
Upper Byte
UB
LB
ZZ
CE
Vcc
GENERAL DESCRIPTION
The UT65L168 is a 8,388,608-bit CMOS random
access memory organized as 524,288 words by 16
bits. It is fabricated using PSEUDO SRAM techniques,
yields high-density and low power consumption
device.
The UT65L168 is design for upper and low byte
access by data byte control ( UB
LB
).It has low
power modes by using control pin
ZZ
.
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A18
Address Inputs
I/O1 - I/O16
Data Inputs/Outputs
CE
Chip enable Input
WE
Write Enable Input
OE
Output Enable Input
LB
Lower Byte Control
UB
Upper Byte Control
ZZ
Low Power Modes
V
CC
Core
Power
Vccq I/O
power
V
SS
Ground
NC No
Connection
PIN CONFIGURATION
A12
A11
A13
I/O9
A10
A14
I/O11
I/O10
A15
I/O6
I/O7
I/O8
A9
Vss
I/O12
A8
A16
I/O5
Vcc
Vccq
I/O4
A17
Vss
I/O13
Vss
NC
A7
A0
I/O3
I/O2
I/O15
I/O14
I/O1
NC
A6
A1
A3
A5
A18
I/O16
A4
A2
1
2
3
4
5
6
H
G
C
D
E
F
A
B
TFBGA
LB
OE
UB
ZZ
CE
WE
UTRON
UT65L168(E)/UT65L168(I)
Rev. 1.1
512K X 16 BITS LOW POWER PSEUDO SRAM
UTRON TECHNOLOGY INC. P80094
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
PIN CONFIGURATION
TSOP-I
I/O7
Vss
I/O14
I/O13
I/O6
I/O12
I/O5
Vcc
I/O4
I/O11
A12
Vss
I/O2
I/O9
I/O3
I/O1
I/O10
I/O8
I/O15
35
36
37
38
39
40
41
42
43
44
45
46
48
32
33
34
29
30
31
27
28
47
25
26
I/O16
A11
CE
OE
A16
A15
A14
A13
A1
A0
NC
ZZb
A8
NC
NC
14
13
12
11
10
9
8
7
6
5
4
3
1
17
16
15
20
19
18
22
21
A7
A17
A6
A5
A4
A18
A9
2
24
23
A3
A2
WE
LB
UB
A10
NC
UT65L168
ABSOLUTE MAXIMUM RATINGS*
PARAMETER SYMBOL
RATING
UNIT
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-0.2 to Vcc+0.3
V
Voltage on Vcc supply relative to V
SS
V
CC
-0.2 to 4.2
V
Extended
T
A
-25 to 80
Operating Temperature
Industrial T
A
-40 to 85
Storage Temperature
T
STG
-65 to +150
Power Dissipation
P
D
1.0 W
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
I/O OPERATION
MODE
CE
OE
WE
LB
UB
ZZ
I/O1-I/O8 I/O9-I/O16
SUPPLY CURRENT
Standby
H
X
X
X
X
H
High Z
High Z
I
SB
, I
SB1
Output Disable
L
L
H
H
H
H
L
X
X
L
H
H
High Z
High Z
I
CC
,I
CC1
,I
CC2
Read
L
L
L
L
L
L
H
H
H
L
H
L
H
L
L
H
H
H
D
OUT
High Z
D
OUT
High Z
D
OUT
D
OUT
I
CC
,I
CC1
,I
CC2
Write
L
L
L
X
X
X
L
L
L
L
H
L
H
L
L
H
H
H
D
IN
High Z
D
IN
High Z
D
IN
D
IN
I
CC
,I
CC1
,I
CC2
Deep Power Down
X
X
X
X
X
L
High Z
High Z
I
SB0
Note: H = V
IH
, L=V
IL
, X = Don't care.
UTRON
UT65L168(E)/UT65L168(I)
Rev. 1.1
512K X 16 BITS LOW POWER PSEUDO SRAM
UTRON TECHNOLOGY INC. P80094
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.5V~3.3V)
PARAMETER SYMBOL
TEST
CONDITION
MIN.
TYP.
MAX.
UNIT
Power Voltage
V
CC
2.5 3.0
3.3
V
I/O operating voltage
Vccq
2.5 3.0
3.3
V
Input High Voltage
V
IH
*1*3
2.2
-
V
CC
+0.2 V
Input Low Voltage
V
IL
*2*3
-0.2 -
0.4
V
Input Leakage Current
I
LI
V
SS
V
IN
V
CC
-
1
-
1
A
Output Leakage Current
I
LO
V
SS
V
I/O
V
CC;
Output Disable
- 1
-
1
A
Output High Voltage
V
OH
I
OH
= -1mA
2.2
2.7
-
V
Output Low Voltage
V
OL
I
OL
= 2mA
-
-
0.4
V
Icc
Cycle time=Min,100%duty, I
I/O
=0mA
CE
=V
IL
,
ZZ
= V
IH
, V
IN
=V
IL
or
V
IH
- 20 30
mA
Average Operating
Current
Icc1
Cycle time=1s,100%duty, I
I/O
=0mA
CE
0.2V,
ZZ
= V
IH
V
IN
0.2V or V
IN
Vcc-0.2V
- - 7
mA
Standby Current (TTL)
I
SB
CE
=
ZZ
=V
IH,
other inputs =V
IL
or V
IH
- - 0.3
mA
Standby Current (CMOS)
I
SB1
CE
Vcc-0.2 ,
ZZ
Vcc-0.2V
other inputs = 0 ~ Vcc
LL
- 50 70
A
Deep Power Down
I
SB0
ZZ
0.2V, other pins = 0 ~ Vcc
No refresh
LL - - 10
A
Note :
*1.Overshoot : Vcc+1.0V in case of pulse width 20ns.
*2.Undershoot : -1.0V in case of pulse width 20ns.
*3.Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE
(T
A
=25, f=1.0MHz)
PARAMETER
SYMBOL
MIN.
MAX
UNIT
Input Capacitance
C
IN
-
8 pF
Input/Output Capacitance
C
I/O
-
8 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
UTRON
UT65L168(E)/UT65L168(I)
Rev. 1.1
512K X 16 BITS LOW POWER PSEUDO SRAM
UTRON TECHNOLOGY INC. P80094
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
AC TEST CONDITIONS
Input Pulse Levels
0.2V to 2.4V
Input Rise and Fall Times
5ns
Input and Output Timing Reference Levels
1.5V
Output Load
C
L
= 30pF+1TTL, I
OH
/I
OL
= -1mA / 2mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
=2.5V~3.3V)
(1) READ CYCLE
UT65L168-60 UT65L168-70
PARAMETER SYMBOL
MIN. MAX. MIN. MAX.
UNIT
Read Cycle Time
t
RC
60 40k 70 40k ns
Address Access Time
t
AA
- 60 - 70 ns
Chip enable to output
t
ACE
- 60 - 70 ns
Output Enable to Valid Output
t
OE
- 25 - 25 ns
Chip enable to Low-Z output
t
CLZ
10 - 10 - ns
Output Enable to Low-Z Output
t
OLZ
5 - 5 - ns
Chip Disable to High-Z Output
t
CHZ
0 5 0 5 ns
Output Disable to High-Z Output
t
OHZ
0 5 0 5 ns
Output Hold from Address Change
t
OH
5 - 5 - ns
LB
,
UB
Access Time
t
BA
- 60 - 70 ns
LB
,
UB
Disable
to High-Z Output
t
BHZ
0 5 0 5 ns
LB
,
UB
Enable
to Low-Z Output
t
BLZ
10 - 10 - ns
(2) WRITE CYCLE
UT65L168-60 UT65L168-70
PARAMETER SYMBOL
MIN. MAX. MIN. MAX.
UNIT
Write Cycle Time
t
WC
60 40k 70 40k ns
Address Valid to End of Write
t
AW
50 - 60 - ns
Chip enable to End of Write
t
CW
50 - 60 - ns
Address Set-up Time
t
AS
0 - 0 - ns
Write Pulse Width
t
WP
50 - 50 - ns
Write Recovery Time
t
WR
0 - 0 - ns
Data to Write Time Overlap
t
DW
20 - 20 - ns
Data Hold from Write Time
t
DH
0 - 0 - ns
End Write to Output Low-Z
t
OW
5 - 5 - ns
Write to Output High Z
t
WHZ
0 5 0 5 ns
LB
,
UB
Valid to End of Write
t
BW
50 - 60 - ns
(3) PAGE MODE CYCLE
UT65L168-60 UT65L168-70
PARAMETER SYMBOL
MIN. MAX. MIN. MAX.
UNIT
Page Mode Cycle Time
t
PC
25 - 25 - ns
Page Mode Address Access Time
t
PAA
- 25 - 25 ns
Maximum Cycle Time
t
MRC
- 40k - 40k ns
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