SPICE Device Model SUD19P06-60L
Vishay Siliconix
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 73154
www.vishay.com
29-Sep-04
1
P-Channel 60-V (D-S) 175
C MOSFET
CHARACTERISTICS
P-Channel Vertical DMOS
Macro Model (Subcircuit Model)
Level 3 MOS
Apply for both Linear and Switching Application
Accurate over the -55 to 125C Temperature Range
Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the p-channel vertical DMOS. The subcircuit
model is extracted and optimized over the
-55 to 125C
temperature ranges under the pulsed 0 to 10V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched C
gd
model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
SPICE Device Model SUD19P06-60L
Vishay Siliconix
www.vishay.com
Document Number: 73154
2
29-Sep-04
SPECIFICATIONS (T
J
= 25
C UNLESS OTHERWISE NOTED)
Parameter Symbol
Test
Conditions
Simulated
Data
Measured
Data
Unit
Static
Gate Threshold Voltage
V
GS(th)
V
DS
= V
GS
, I
D
=
-250 A
2
V
On-State Drain Current
a
I
D(on)
V
DS
=
-5 V, V
GS
=
-10 V
104 A
V
GS
=
-10 V, I
D
=
-10 A
0.047 0.047
V
GS
=
-10 V, I
D
=
-10 A, T
J
= 125
C
0.083
V
GS
=
-10 V, I
D
=
-10 A, T
J
= 175
C
0.102
Drain-Source On-State Resistance
a
r
DS(on)
V
GS
=
-4.5 V, I
D
=
-5 A
0.060 0.061
Forward Transconductance
a
g
fs
V
DS
=
-15 V, I
D
=
-10 A
20 22
S
Diode Forward Voltage
a
V
SD
I
S
=
-10 A, V
GS
= 0 V
- 0.87
- 1
V
Dynamic
b
Input Capacitance
C
iss
1430
1140
Output Capacitance
C
oss
130
130
Reverse Transfer Capacitance
C
rss
V
GS
= 0 V, V
DS
=
-25 V, f = 1 MHz
84 90
pF
Total Gate Charge
c
Q
g
25
26
Gate-Source Charge
c
Q
gs
4.5
4.5
Gate-Drain Charge
c
Q
gd
V
DS
=
-30 V, V
GS
=
-10 V, I
D
=
-10 A
7 7
nC
Notes
a. Pulse test; pulse width
300 s, duty cycle 2%.
b. Guaranteed by design, not subject to production testing.
c. Independent of operating temperature.
SPICE Device Model SUD19P06-60L
Vishay Siliconix
Document Number: 73154
www.vishay.com
29-Sep-04
3
COMPARISON OF MODEL WITH MEASURED DATA (T
J
=25
C UNLESS OTHERWISE NOTED)
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