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Электронный компонент: VT6305

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VT6305
PCI 1394 Host Controller
1394.A OHCI Link Layer Controller
for the PCI Bus
Revision 0.2
March 10, 2000
VIA TECHNOLOGIES, INC.
Copyright Notice:
Copyright
1998 VIA Technologies Incorporated. Printed in the United States. A
LL
R
IGHTS
R
ESERVED
.
No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into
any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise
without the prior written permission of VIA Technologies Incorporated.
VT6305 may only be used to identify a product of VIA Technologies, Inc.
is a registered trademark of VIA Technologies, Incorporated.
Windows 95
TM
, Windows 98
TM
, Windows NT
TM
, and Plug and Play
TM
are registered trademarks of Microsoft Corp.
PCI
TM
is a registered trademark of the PCI Special Interest Group.
All trademarks are the properties of their respective owners.
Disclaimer Notice:
No license is granted, implied or otherwise, under any patent or patent rights of VIA Technologies. VIA Technologies
makes no warranties, implied or otherwise, in regard to this document and to the products described in this document.
The information provided by this document is believed to be accurate and reliable to the publication date of this
document. However, VIA Technologies assumes no responsibility for any errors in this document. Furthermore, VIA
Technologies assumes no responsibility for the use or misuse of the information in this document and for any patent
infringements that may arise from the use of this document. The information and product specifications within this
document are subject to change at any time, without notice and without obligation to notify any person of such
change.
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th
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Fremont, CA
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Tel:
(510) 683-3300
Tel:
(886-2) 218-5452
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Fax:
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or-
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BBS:
886-2-2185208
Revision 0.2
March 10, 2000
-i-
Revision History
Technologies, Inc.
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R
EVISION
H
ISTORY
Document Release
Date
Revision
Initial
s
Revision 0.1
5/19/98
Initial release as VT83C574
DH
Revision 0.2
7/31/98
Changed part # to VT6305
Revised pinouts and added pin descriptions
DH
Revision 0.2
March 10, 2000
-
ii-
Table of Contents
Technologies, Inc.
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T
ABLE OF
C
ONTENTS
REVISION HISTORY................................................................................................................................................................I
TABLE OF CONTENTS.......................................................................................................................................................... II
LIST OF FIGURES .................................................................................................................................................................III
LIST OF TABLES ...................................................................................................................................................................III
OVERVIEW .............................................................................................................................................................................. 2
PINOUTS ................................................................................................................................................................................... 3
P
IN
D
IAGRAM
......................................................................................................................................................................... 3
P
IN
L
IST
................................................................................................................................................................................. 4
P
IN
D
ESCRIPTIONS
................................................................................................................................................................. 5
REGISTERS .............................................................................................................................................................................. 8
R
EGISTER
O
VERVIEW
............................................................................................................................................................ 8
R
EGISTER
D
ESCRIPTIONS
..................................................................................................................................................... 11
1394 Host Controller Configuration Registers (Function 0) ........................................................................................ 11
Configuration Space Header ......................................................................................................................................................... 11
Controller-Specific Configuration Registers.................................................................................................................................. 13
1394 Host Controller Memory-Space Registers ........................................................................................................... 14
Autonomous CSR Resources ........................................................................................................................................................ 15
Bus Management CSR Registers .................................................................................................................................................. 15
HC Control Registers ................................................................................................................................................................... 17
Self-ID Control Registers ............................................................................................................................................................. 18
Channel Mask Registers............................................................................................................................................................... 18
Interrupt Registers........................................................................................................................................................................ 19
Link Control Registers ................................................................................................................................................................. 21
PHY Control Registers................................................................................................................................................................. 22
Cycle Timer Registers .................................................................................................................................................................. 22
Filter Registers ............................................................................................................................................................................ 23
Asynchronous Transmit & Receive Context Registers................................................................................................................... 24
Isochronous Transmit Context Registers ....................................................................................................................................... 26
Isochronous Receive Context Registers......................................................................................................................................... 27
ELECTRICAL SPECIFICATIONS........................................................................................................................................ 29
A
BSOLUTE
M
AXIMUM
R
ATINGS
........................................................................................................................................... 29
DC C
HARACTERISTICS
........................................................................................................................................................ 29
PACKAGE MECHANICAL SPECIFICATIONS .................................................................................................................. 30
Revision 0.2
March 10, 2000
-iii-
List of Figures & Tables
Technologies, Inc.
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L
IST OF
F
IGURES
FIGURE 1. VT6305 CHIP BLOCK DIAGRAM ..................................................................................................................... 2
FIGURE 2. VT6305 PIN DIAGRAM (TOP VIEW) ................................................................................................................ 3
FIGURE 3. VT6305 PIN LIST (ALPHABETICAL ORDER)................................................................................................. 4
FIGURE 4. MECHANICAL SPECIFICATIONS 128 PIN PQFP PACKAGE ................................................................. 30
L
IST OF
T
ABLES
TABLE 1. VT6305 PIN DESCRIPTIONS ............................................................................................................................... 5
TABLE 2. REGISTERS ........................................................................................................................................................... 8
TABLE 3. PACKET EVENT CODES ................................................................................................................................... 25