VIA Technologies, Inc.
Preliminary VT6508 Datasheet
2
P
RELIMINARY
R
ELEASE
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LL
R
IGHTS
R
ESERVED
.
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VIA Technologies, Inc.
Preliminary VT6508 Datasheet
3
T
ABLE OF
C
ONTENTS
T
ABLE OF
C
ONTENTS
................................................................................................................................ 3
F
IGURES AND
T
ABLES
............................................................................................................................... 4
R
EVERSION
H
ISTORY
................................................................................................................................ 5
F
EATURES
................................................................................................................................................ 6
B
LOCK
D
IAGRAM
...................................................................................................................................... 9
FIGURE 1: FUNCTION BLOCK DIAGRAM OF VT6508. (NOTE THAT SOME INTERFACE
SIGNALS ARE ONLY AVAILABLE IN VT6509 OF 208-PIN PQFP PACKAGE.).............................. 9
P
INOUT
D
IAGRAM
................................................................................................................................... 10
FIGURE 2: PINOUT DIAGRAM OF VT6508. ...................................................................................... 10
P
IN
D
ESCRIPTIONS
.................................................................................................................................. 11
D
EFINITION OF
VT6508B S
TRAPPING
P
INS
.............................................................................................. 12
Pin.................................................................................................................................................... 12
SRAM TYPE: .................................................................................................................................... 12
SECTION I FUNCTIONAL DESCRIPTIONS...................................................................................... 15
1 G
ENERAL
D
ESCRIPTION
...................................................................................................................... 15
2 T
HE
VIA E
THER
S
WITCH
A
RCHITECTURE
............................................................................................ 15
2.1 Switch initialization procedures .................................................................................................. 15
2.2 Packet Switching Flow ................................................................................................................ 16
2.3 P
ACKET
B
UFFERS AND
F
ORWARDING
T
ABLE
...................................................................................... 16
FIGURE 3. SRAM MEMORY LAYOUT............................................................................................... 17
FIGURE 4. DATA STRUCTURE OF FORWARDING TABLE SLOT................................................ 17
FIGURE 5. DATA STRUCTURE OF EMBEDDED LINK NODE. ...................................................... 17
2.3 RMII I
NTERFACE
.............................................................................................................................. 19
2.3 M
ANAGEMENT
I
NTERFACE AND
A
UTO
N
EGOTIATION
......................................................................... 19
2.4 F
LOW
C
ONTROL
............................................................................................................................... 21
FIGURE 6. XON/XOFF WINDOW CONCEPT..................................................................................... 23
2.5 B
ROADCAST
S
TORM
F
ILTERING
......................................................................................................... 27
2.6 S
ERIAL
EEPROM
INTERFACE AND
C
ONFIGURATION COMMANDS
........................................................ 27
2.7 T
RUNKING
....................................................................................................................................... 28
3
T
HE
VT6508 SRAM ADDRESS MAPPING TABLE ............................................................... 30
SECTION II REGISTER MAP............................................................................................................... 31
1. R
EGISTERS
T
ABLE
............................................................................................................................. 31
SECTION III ELECTRICAL SPECIFICATIONS................................................................................. 45
A
BSOLUTE
M
AXIMUM
R
ATINGS
............................................................................................................... 45
DC C
HARACTERISTICS
............................................................................................................................ 45
AC C
HARACTERISTICS
............................................................................................................................ 46
P
ACKAGE
M
ECHANICAL
S
PECIFICATIONS
................................................................................................. 48
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