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VT82C580VPX
Preliminary Revision 0.1 January 9, 1997
-i-
Revision History
R
EVISION
H
ISTORY
Document Release
Date
Revision
Initials
Preliminary
1/2/97
Original release based on VT82C595 Apollo VP2 data sheet revision 0.4
(VPX register set is more like Apollo VP2 than like VT82C580 Apollo VP)
Changed intro and features list to reflect Apollo VPX
Added pinouts, electrical, and mechanical specs from 580VP data sheet
Added tables of pins in alphabetical order for both chips
Changed pinouts to reflect VPX
- Removed UMA (added CPURSTI and CPURSTO on MREQ0/1#)
- Added 64Mb DRAM support (added MA12/13 opt on MBEN/RAS5)
- Improved SDRAM support (added SWEC#/SCASC# on WE/Mgnt)
Changed registers to reflect VPX
- Removed ECC registers (no pins for ECC in PQFP package)
- Added Rx50[2], Rx65[2], Rx66[5], Rx68[3], Rx6B[2]
- Swapped bytes of Rx54-55 & 56-57 to match silicon (same in VP2)
DH
9,$7HFKQRORJLHV,QF
VT82C580VPX
Preliminary Revision 0.1 January 9, 1997
-ii-
Table of Contents
T
ABLE OF
C
ONTENTS
REVISION HISTORY........................................................................................................................................................................I
TABLE OF CONTENTS .................................................................................................................................................................. II
LIST OF FIGURES..........................................................................................................................................................................III
LIST OF TABLES ...........................................................................................................................................................................IV
OVERVIEW ....................................................................................................................................................................................... 3
PINOUTS ............................................................................................................................................................................................ 5
VT82C585VPX P
INOUTS
.............................................................................................................................................................. 5
VT82C587VP P
INOUTS
............................................................................................................................................................... 11
REGISTERS ..................................................................................................................................................................................... 14
R
EGISTER
O
VERVIEW
................................................................................................................................................................. 14
C
ONFIGURATION
S
PACE
I/O ....................................................................................................................................................... 15
R
EGISTER
D
ESCRIPTIONS
............................................................................................................................................................ 16
PCI Configuration Space Header........................................................................................................................................ 16
VT82C585VPX-Specific Configuration Registers ............................................................................................................. 17
Cache Control ....................................................................................................................................................................................... 17
DRAM Control ..................................................................................................................................................................................... 19
PCI Bus Control.................................................................................................................................................................................... 23
ELECTRICAL SPECIFICATIONS ............................................................................................................................................... 25
A
BSOLUTE
M
AXIMUM
R
ATINGS
................................................................................................................................................. 25
DC C
HARACTERISTICS
................................................................................................................................................................ 25
AC T
IMING
S
PECIFICATIONS
...................................................................................................................................................... 26
PACKAGE MECHANICAL SPECIFICATIONS ........................................................................................................................ 49
PQFP-208 .................................................................................................................................................................................... 49
PQFP-100 .................................................................................................................................................................................... 50
9,$7HFKQRORJLHV,QF
VT82C580VPX
Preliminary Revision 0.1 January 9, 1997
-iii-
List of Figures
L
IST OF
F
IGURES
FIGURE 1. APOLLO VPX SYSTEM BLOCK DIAGRAM ......................................................................................................... 3
FIGURE 2. VT82C585VPX PIN DIAGRAM (TOP VIEW) ......................................................................................................... 5
FIGURE 3. VT82C585VPX PIN LIST (ALPHABETICAL ORDER) ......................................................................................... 6
FIGURE 4. VT82C587VP PIN DIAGRAM (TOP VIEW) .......................................................................................................... 11
FIGURE 5. VT82C587VP PIN LIST (ALPHABETICAL ORDER) .......................................................................................... 12
FIGURE 6. DRAM READ PIPE LINE EDO 5-2-2-2, 3-2-2-2 .................................................................................................... 30
FIGURE 7. POST WRITE 3111,DRAM EDO 2222 .................................................................................................................... 31
FIGURE 8. SDRAM READ CYCLE (BANK INTERLEAVE, CAS LATENCY=3) ................................................................ 32
FIGURE 9. SDRAM WRITE CYCLE (BANK INTERLEAVE) ................................................................................................ 33
FIGURE 10. CPU READ HIT SYNCHRONOUS SRAM 3111 .................................................................................................. 34
FIGURE 11. CPU WRITE HIT SYNCHRONOUS SRAM 3111................................................................................................ 35
FIGURE 12. CPU READ MISS FILL SYNCHRONOUS SRAM .............................................................................................. 36
FIGURE 13. CPU READ MISS DIRTY L2 WRITE BACK FILL............................................................................................. 37
FIGURE 14. CPU READ PCI SLAVE .......................................................................................................................................... 38
FIGURE 15. CPU WRITE PCI SLAVE WRITE BUFFER ON FAST BACK TO BACK ...................................................... 39
FIGURE 16. PCI MASTER READ HIT DRAM.......................................................................................................................... 40
FIGURE 17. PCI MASTER READ L1 SNOOP TO DRAM....................................................................................................... 41
FIGURE 18. PCI MASTER READ HIT L2 ................................................................................................................................. 42
FIGURE 19. PCI MASTER READ L1 SNOOP TO L2............................................................................................................... 43
FIGURE 20. PCI MASTER WRITE DRAM ............................................................................................................................... 44
FIGURE 21. PCI MASTER WRITE HIT L1 SNOOP TO DRAM ............................................................................................ 45
FIGURE 22. PCI MASTER WRITE HIT L2 ............................................................................................................................... 46
FIGURE 23. PCI MASTER WRITE HIT L2, L1 HITM ............................................................................................................ 47
FIGURE 24. PCI MASTER WRITE HIT L2 & DIRTY ............................................................................................................. 48
FIGURE 25. MECHANICAL SPECIFICATIONS - 208-PIN PLASTIC FLAT PACKAGE.................................................. 49
FIGURE 26. MECHANICAL SPECIFICATIONS - 100-PIN PLASTIC FLAT PACKAGE.................................................. 50
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