H
FRQQHFW
Z
97
$SROOR3UR0HGLD
0+]
6LQJOH&KLS6ORW6RFNHW3&,1RUWK%ULGJH
:LWK,QWHJUDWHG$*3''*UDSKLFV$FFHOHUDWRU
DQG$GYDQFHG0HPRU\&RQWUROOHU
VXSSRUWLQJ3&3&DQG9&06'5$0
IRU'HVNWRS3&6\VWHPV
5HYLVLRQ
6HSWHPEHU
9,$7(&+12/2*,(6,1&
&RS\ULJKW1RWLFH
&RS\ULJKW
9,$ 7HFKQRORJLHV ,QFRUSRUDWHG 3ULQWHG LQ WKH 8QLWHG 6WDWHV $
//
5
,*+76
5
(6(59('
1R SDUW RI WKLV GRFXPHQW PD\ EH UHSURGXFHG WUDQVPLWWHG WUDQVFULEHG VWRUHG LQ D UHWULHYDO V\VWHP RU WUDQVODWHG LQWR
DQ\ ODQJXDJH LQ DQ\ IRUP RU E\ DQ\ PHDQV HOHFWURQLF PHFKDQLFDO PDJQHWLF RSWLFDO FKHPLFDO PDQXDO RU RWKHUZLVH
ZLWKRXW WKH SULRU ZULWWHQ SHUPLVVLRQ RI 9,$ 7HFKQRORJLHV ,QFRUSRUDWHG
97&% 97&% 97&$ 97& 97&093 97 97& 97& 97&
97&$ 97& 97&$ 97&; 97 0RELOH 6RXWK 6XSHU 6RXWK $SROOR 093 $SROOR 093
$SROOR 3UR $SROOR 3UR3OXV $SROOR 3UR $SROOR 3UR$ DQG $SROOR 3UR0HGLD PD\ RQO\ EH XVHG WR LGHQWLI\ SURGXFWV
RI 9,$ 7HFKQRORJLHV
36
%
LV D UHJLVWHUHG WUDGHPDUN RI ,QWHUQDWLRQDO %XVLQHVV 0DFKLQHV &RUS
&HOHURQ 3HQWLXP
%
3HQWLXP,,
%
3HQWLXP,,,
%
00;
%
DQG ,QWHO DUH UHJLVWHUHG WUDGHPDUNV RI ,QWHO &RUS
&\UL[
;
%
LV D UHJLVWHUHG WUDGHPDUN RI &\UL[ &RUS
$0'
.
%
$0'.
%
DQG $0'.
%
DUH UHJLVWHUHG WUDGHPDUNV RI $GYDQFHG 0LFUR 'HYLFHV &RUS
:LQGRZV
%
:LQGRZV
%
DQG 3OXJ DQG 3OD\
%
DUH UHJLVWHUHG WUDGHPDUNV RI 0LFURVRIW &RUS
3&,
%
LV D UHJLVWHUHG WUDGHPDUN RI WKH 3&, 6SHFLDO ,QWHUHVW *URXS
$OO WUDGHPDUNV DUH WKH SURSHUWLHV RI WKHLU UHVSHFWLYH RZQHUV
'LVFODLPHU1RWLFH
1R OLFHQVH LV JUDQWHG LPSOLHG RU RWKHUZLVH XQGHU DQ\ SDWHQW RU SDWHQW ULJKWV RI 9,$ 7HFKQRORJLHV 9,$ 7HFKQRORJLHV
PDNHV QR ZDUUDQWLHV LPSOLHG RU RWKHUZLVH LQ UHJDUG WR WKLV GRFXPHQW DQG WR WKH SURGXFWV GHVFULEHG LQ WKLV GRFXPHQW
7KH LQIRUPDWLRQ SURYLGHG E\ WKLV GRFXPHQW LV EHOLHYHG WR EH DFFXUDWH DQG UHOLDEOH WR WKH SXEOLFDWLRQ GDWH RI WKLV
GRFXPHQW +RZHYHU 9,$ 7HFKQRORJLHV DVVXPHV QR UHVSRQVLELOLW\ IRU DQ\ HUURUV LQ WKLV GRFXPHQW )XUWKHUPRUH 9,$
7HFKQRORJLHV DVVXPHV QR UHVSRQVLELOLW\ IRU WKH XVH RU PLVXVH RI WKH LQIRUPDWLRQ LQ WKLV GRFXPHQW DQG IRU DQ\ SDWHQW
LQIULQJHPHQWV WKDW PD\ DULVH IURP WKH XVH RI WKLV GRFXPHQW 7KH LQIRUPDWLRQ DQG SURGXFW VSHFLILFDWLRQV ZLWKLQ WKLV
GRFXPHQW DUH VXEMHFW WR FKDQJH DW DQ\ WLPH ZLWKRXW QRWLFH DQG ZLWKRXW REOLJDWLRQ WR QRWLI\ DQ\ SHUVRQ RI VXFK FKDQJH
2IILFHV
86$ 2IILFH
7DLSHL 2IILFH
0LVVLRQ &RXUW
WK
)ORRU 1R
)UHPRQW &$
&KXQJ&KHQJ 5RDG +VLQ7LHQ
86$
7DLSHL 7DLZDQ 52&
7HO
7HO
)D[
)D[
2QOLQH6HUYLFHV
+RPH 3DJH
http://www.via.com.tw
7DLZDQ RU
http://www.viatech.com
86$
)73 6HUYHU
ftp.via.com.tw
7DLZDQ
%%6
VT8601 Apollo ProMedia
Revision 1.3 September 8, 1999
-i-
Revision History
7HFKQRORJLHV ,QF
:H &
:H &RRQQQQHFW
HFW
R
EVISION
H
ISTORY
Document Release
Date
Revision
Initials
0.92
12/9/98
Initial internal release based on Apollo MVP4 data sheet revision 0.92
Added preliminary pin diagram based on engineering ballout rev 0.3 11/10/98
Added Slot-1 pinouts from Apollo Pro Plus Data Sheet
Replaced feature list, overview, and vblock diagram from product brief
DH
0.93
12/16/98
Updated pinouts to match engineering rev 0.5 document dated 12/1/98
DH
0.94
1/20/99
Updated pinouts to match engineering rev 0.8 document dated 12/22/98
DH
1.0
6/4/99
Added 133 MHz Support to Feature Bullets
Updated / Fixed Pin Descriptions:
Fixed description of strap options on MA2, MA8, and MA11-14
Removed Auxiliary Memory Port
Added REQ/GNT[4-7]#
Added GND & VCC3 pins to increase pin count to 510 (updated mech spec)
Fixed definitions of RESET# & CRSTI# and changed CRSTI# to CPURSTD#
Removed PWRGD function from SERR#
Fixed definitions of SRAS#, SCAS#, and SWE#
Added note to PLLTST description
Updated Device 0 Registers Rx50-53, 68[4], 69, 6B[5-1], 6C[7-4], 70[3,0,
72[0], 76[7], 79[1-0], 7A (added)
Updated Device 1 Registers Rx41[0], 42[0]
DH
1.1
6/23/99
Updated feature bullets & overview and fixed misc formatting problems
Fixed REQ/GNT4# pinouts and CKE & DQM naming polarity
Device 0 Bus 0 updated Rx2-3 Device ID, 69[7-6], 6D[6-5], 76[6]
Device 0 Bus 0 added Rx2C-D, 2E-F, 50[1], 51[5], 53[2], removed 6E-6F
Device 0 Bus 1 updated Rx0-3 Vendor & Device ID, Rx7-6[7]
Removed AC timing specs
DH
1.11
7/8/99
Fixed pin descriptions of CPURSTD# and SUSP
DH
1.2
8/23/99
Fixed typo in device 0 Rx50[7] description; added comment about default state
Fixed system frequency divider settings (MA pin descriptions, Dev 0 Rx68[1-0])
DH
1.3
9/8/99
Fixed strap options on MA2-6 and MA13 pin descriptions
Fixed Device 0 Rx52[7] strap option and removed (reserved) Device 0 Rx52[5]
Removed "VIA Confidential" watermark
DH
VT8601 Apollo ProMedia
Revision 1.3 September 8, 1999
-ii-
Table of Contents
7HFKQRORJLHV ,QF
:H &
:H &RRQQQQHFW
HFW
T
ABLE OF
C
ONTENTS
REVISION HISTORY........................................................................................................................................................................I
TABLE OF CONTENTS .................................................................................................................................................................. II
LIST OF FIGURES..........................................................................................................................................................................IV
LIST OF TABLES ...........................................................................................................................................................................IV
APOLLO PROMEDIA...................................................................................................................................................................... 1
SYSTEM OVERVIEW...................................................................................................................................................................... 6
A
POLLO
P
RO
M
EDIA
C
ORE
L
OGIC
O
VERVIEW
............................................................................................................................ 7
A
POLLO
P
RO
M
EDIA
G
RAPHICS
C
ONTROLLER
O
VERVIEW
........................................................................................................ 8
Capability Overview ............................................................................................................................................................... 8
System Capabilities................................................................................................................................................................. 9
High Performance 64-bit 2D GUI.......................................................................................................................................... 9
Highly Integrated RAMDAC
TM
& Clock Synthesizer......................................................................................................... 9
Full Feature High Performance 3D Engine .......................................................................................................................... 9
Video Processor..................................................................................................................................................................... 10
Video Capture and DVD ...................................................................................................................................................... 10
Versatile Frame Buffer Interface ........................................................................................................................................ 10
Hi-Res and Hi-Ref Display Support .................................................................................................................................... 10
CRT Power Management (VESA DPMS) .......................................................................................................................... 11
Flat Panel Interface .............................................................................................................................................................. 11
Video Capture Interface....................................................................................................................................................... 11
Complete Hardware Compatibility ..................................................................................................................................... 11
PINOUTS .......................................................................................................................................................................................... 12
PIN DESCRIPTIONS ...................................................................................................................................................................... 15
REGISTERS ..................................................................................................................................................................................... 23
R
EGISTER
O
VERVIEW
................................................................................................................................................................. 23
R
EGISTER
S
UMMARY
T
ABLES
..................................................................................................................................................... 23
M
ISCELLANEOUS
I/O................................................................................................................................................................... 33
C
ONFIGURATION
S
PACE
I/O ....................................................................................................................................................... 33
R
EGISTER
D
ESCRIPTIONS
............................................................................................................................................................ 34
Device 0 Bus 0 Header Registers - Host Bridge.................................................................................................................. 34
Device 0 Bus 0 Host Bridge Registers ................................................................................................................................. 36
CPU Interface Control .......................................................................................................................................................................... 36
DRAM Control ..................................................................................................................................................................................... 38
PCI Bus Control.................................................................................................................................................................................... 44
GART / Graphics Aperture Control ...................................................................................................................................................... 48
AGP Control ......................................................................................................................................................................................... 50
Device 1 Bus 0 Header Registers - PCI-to-AGP Bridge .................................................................................................... 52
Device 1 Bus 0 PCI-to-AGP Bridge Registers .................................................................................................................... 54
AGP Bus Control .................................................................................................................................................................................. 54
Device 0 Bus 1 Header Registers - Graphics Accelerator.................................................................................................. 55
Device 0 Bus 1 Graphics Accelerator Registers ................................................................................................................. 58
Graphics Accelerator PCI Bus Master Registers................................................................................................................................... 59
VGA Standard Registers - Introduction ................................................................................................................................................ 65
Capture / ZV Port Registers .................................................................................................................................................................. 66
DVD Registers ...................................................................................................................................................................................... 67
VT8601 Apollo ProMedia
Revision 1.3 September 8, 1999
-iii-
Table of Contents
7HFKQRORJLHV ,QF
:H &
:H &RRQQQQHFW
HFW
VGA Registers....................................................................................................................................................................... 70
Attribute Controller Registers (AR) ...................................................................................................................................................... 70
VGA Status / Enable Registers ............................................................................................................................................................. 70
VGA Sequencer Registers (SR) ............................................................................................................................................................ 71
VGA RAMDAC Registers .................................................................................................................................................................... 71
VGA Graphics Controller Registers (GR)............................................................................................................................................. 72
VGA CRT Controller Registers (CR) .................................................................................................................................................. 73
VGA Extended Registers...................................................................................................................................................... 74
VGA Extended Registers Non-Indexed I/O Ports .............................................................................................................................. 74
VGA Extended Registers Sequencer Indexed .................................................................................................................................... 75
VGA Extended Registers Graphics Controller Indexed ..................................................................................................................... 85
VGA Extended Registers CRT Controller Indexed............................................................................................................................ 91
VGA Extended Registers CRTC Shadow ........................................................................................................................................ 105
3D Graphics Engine Registers ........................................................................................................................................... 106
Operational Concept ........................................................................................................................................................................... 106
Drawing............................................................................................................................................................................................... 107
Geometry Primitives............................................................................................................................................................................ 108
Synchronization .................................................................................................................................................................................. 111
Functional Blocks ............................................................................................................................................................................... 111
Bus Interface ....................................................................................................................................................................................... 111
Span Engine......................................................................................................................................................................... 112
Graphics Engine Core ........................................................................................................................................................ 113
Graphics Engine Organization ............................................................................................................................................................ 116
Setup Engine Registers ....................................................................................................................................................................... 117
Vertex Registers .................................................................................................................................................................................. 118
Rasterization Engine Registers............................................................................................................................................................ 119
Pixel Engine Registers ........................................................................................................................................................................ 126
Texture Engine Registers .................................................................................................................................................................... 132
Memory Interface Registers ................................................................................................................................................................ 134
Data Port Area..................................................................................................................................................................................... 134
FUNCTIONAL DESCRIPTIONS ................................................................................................................................................ 135
S
YSTEM
C
ONFIGURATION
......................................................................................................................................................... 135
DFP Interface Configuration ............................................................................................................................................. 135
G
RAPHICS
C
ONTROLLER
P
OWER
M
ANAGEMENT
................................................................................................................... 136
Power Management States................................................................................................................................................. 136
Power Management Clock Control ................................................................................................................................... 136
Power Management Registers ........................................................................................................................................... 136
ELECTRICAL SPECIFICATIONS ............................................................................................................................................. 137
A
BSOLUTE
M
AXIMUM
R
ATINGS
............................................................................................................................................... 137
DC C
HARACTERISTICS
.............................................................................................................................................................. 137
AC T
IMING
S
PECIFICATIONS
.................................................................................................................................................... 137
MECHANICAL SPECIFICATIONS ........................................................................................................................................... 138
PDF 
ZIP