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VT82C686A

Revision 1.54 February 25, 2000

-i-

Revision History

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EVISION

ISTORY

Document Release

Date

Revision

Initials

Revision 0.1

2/10/98

Initial release based on 82C596 "Mobile South" Data Sheet revision 0.3

Revision 0.2

3/17/98

Updated features, overview, pins, regs; Added pin list, Sup-IO, HWM, audio

Revision 0.3

4/20/98

Revised pinouts, fixed TC, changed reg defs, added regs in funcs 1, 3, & 4:

Revision 0.4

4/29/98

Corrected TC, features, pin descriptions, f4/game port regs, removed timing

Revision 0.5

5/27/98

Updated feature bullets, pinouts, registers in functions 0-4 and I/O

Revision 0.6

5/29/98

Updated registers in functions 1, 3, and 4

Revision 0.72

12/1/98

Changed name to 686A, updated feature bullets, pin names, & register defs

Revision 0.8

12/7/98

Updated register definitions

Revision 0.9

12/9/98

Updated register definitions

Revision 1.0

1/15/99

Corrected feature bullets, pin typos, ROMCS# description, f0Rx8, f4Rx2

Revision 1.1

4/15/99

Fixed block diagram, pinouts, register descriptions and electrical specs

Revision 1.23

5/17/99

Fixed GPI1,5,6, GPO1-3,6, PCS0#, DRQ2/DACK2#, MCCS#, PCS0#,

GPO0/SLOWCLK, GPIOA-D, DACK0-7# IRQ option, FDC on LPT

Fixed SuperIO RxF0-1,F6; FDCIObase+1,Fn0Rx43,59,5B-C,68,74-7F,80,88,

88,8A-F,Fn1Rx43,45,54,Fn2&3Rx8,41,42,Fn4Rx54,D2,PMUIORx0,20,
22,24,28/2A,2C,38,40,42,44-5,HWMIORx28-29,35-38,Fn5Rx6,2C,42,48

Revision 1.24

6/18/99

Changed DRVEN to DRVDEN, moved PME# from W11 to T11
MCCS# on U5, SCIOUT# on U8 for "CF" (opposite prior to "CF")
Fixed F0 Rx42,74,76, F1 Rx43, F5/6 Rx48, PMU I/O Rx44

Revision 1.3

6/25/99

Rev 1.3x created to document CD/CE only (info on version CF removed)

Revision 1.4

6/25/99

Updated U5/U8 pin defs; fixed Rx74[5,7],76[4-3],77[0],PMUIO Rx44[5,3-1]

Revision 1.42

7/7/99

Fixed typo in SUSST1# pin description; Fixed Super-I/O RxF8 table
Modified F0 Rx59, F1 Rx6,9,34,3C,41,54,71-75,79-7D,C0-C7, F2/3 Rx41-

42,80-84, F4 Rx4C[0], PMU I/O Rx4[0],20-21[1],22-23[1],24-25[1],2C-
2D[3], HWM IO Rx42[2-1],44[2-1], F5/6 Rx4A-4B, IO Base 0 Rx12[6]

Revision 1.43

10/7/99

Fixed typo in PDIOR#/SDIOR# pin descriptions & Func 4 Rx42[4]

Revision 1.45

12/3/99

Added SCIOUT# to GPIO11 (pin U8), fixed typos in CHAS pin description
Fixed typos in Serial Port 2 register descriptions, changed to new logo format

Revision 1.5

12/21/99

Changed FDC "OD" pin types to "O"; fixed table 2 ECP port address range
Fixed register summary tables: SuperIO Cfg E2; FDC 4, 7
Fixed reg descriptions: SuperIO Cfg E2 & EE defaults; FDCbase+4 & +7;

LPTbase+402; COM1/2 index value references; Com1/2 Divisor offset

Revision 1.51

1/7/00

Changed silicon version CF to CF/CG (CG same programming / pinout as CF)
Fixed IR description (no 3

serial port muxed on COM2)

Fixed Parallel Port I/O Index, FDC I/O index & Base+7 register description
Fixed typo in Func 4 Rx48 description
Changed Pwr Mgmt I/O Rx44[3-2] (different for CD/DE & CF/CG silicon)

Revision 1.52

1/17/00

Added internal I/O APIC pin names; fixed LID name polarity in pin diagram
Corrected F0 Rx41[6],58,74[7],77[4], F1 Rx54[5], F2/3 Rx43, F4

Rx4D[3],54[3-2],55[2], PMU IO Rx0[8], added APIC regs

Revision 1.53

2/8/00

Fixed feature bullet typos, APIC/GPI/GPO pin descriptions, F0 Rx76[4],77[4]
Fixed Func 5/6 AC97 reg summary tables; KBC Ctrl bit-3 changed to reserved

Revision 1.54

2/25/00

Fixed pin direction for APICD0-1 pins (changed from O to IO)
Fixed defaults in register tables for Func 1 Rx40, 41, 43, 45, 50
Added notea to F0 Rx41[3] & Rx45; fixed F1 Rx45[1-0] & misc typos

VT82C686A

Revision 1.54 February 25, 2000

-ii-

Table of Contents

7HFKQRORJLHV ,QF

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ABLE OF

ONTENTS

REVISION HISTORY........................................................................................................................................................................I

TABLE OF CONTENTS .................................................................................................................................................................. II

LIST OF FIGURES..........................................................................................................................................................................IV

LIST OF TABLES ...........................................................................................................................................................................IV

OVERVIEW ....................................................................................................................................................................................... 4

PINOUTS ............................................................................................................................................................................................ 6

IAGRAM

................................................................................................................................................................................. 6

ISTS

........................................................................................................................................................................................ 7

ESCRIPTIONS

......................................................................................................................................................................... 9

REGISTERS ..................................................................................................................................................................................... 27

EGISTER

VERVIEW

................................................................................................................................................................. 27

EGISTER

ESCRIPTIONS

............................................................................................................................................................ 39

Legacy I/O Ports ................................................................................................................................................................... 39

Keyboard Controller Registers.............................................................................................................................................................. 40
DMA Controller I/O Registers .............................................................................................................................................................. 42
Interrupt Controller Registers ............................................................................................................................................................... 43
Timer / Counter Registers ..................................................................................................................................................................... 43
CMOS / RTC Registers......................................................................................................................................................................... 44

Super-I/O Configuration Index / Data Registers ............................................................................................................... 45
Super-I/O Configuration Registers ..................................................................................................................................... 45
Super-I/O I/O Ports .............................................................................................................................................................. 48

Floppy Disk Controller Registers.......................................................................................................................................................... 48
Parallel Port Registers ........................................................................................................................................................................... 49
Serial Port 1 Registers........................................................................................................................................................................... 50
Serial Port 2 Registers........................................................................................................................................................................... 51

SoundBlaster Pro Port Registers......................................................................................................................................... 52

FM Registers ......................................................................................................................................................................................... 52
Mixer Registers ..................................................................................................................................................................................... 52
Sound Processor Registers .................................................................................................................................................................... 52

Game Port Registers ............................................................................................................................................................. 53
PCI Configuration Space I/O............................................................................................................................................... 54
Function 0 Registers - PCI to ISA Bridge........................................................................................................................... 55

PCI Configuration Space Header .......................................................................................................................................................... 55
ISA Bus Control.................................................................................................................................................................................... 55
Plug and Play Control ........................................................................................................................................................................... 59
Distributed DMA / Serial IRQ Control ................................................................................................................................................. 61
Miscellaneous / General Purpose I/O.................................................................................................................................................... 62

Function 1 Registers - Enhanced IDE Controller .............................................................................................................. 68

Function 2 Registers - USB Controller Ports 0-1 ............................................................................................................... 76

Function 3 Registers - USB Controller Ports 2-3 ............................................................................................................... 79

VT82C686A

Revision 1.54 February 25, 2000

-iii-

Table of Contents

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Function 4 Regs - Power Management, SMBus and HWM.............................................................................................. 82

PCI Configuration Space Header .......................................................................................................................................................... 82
Power Management-Specific PCI Configuration Registers .................................................................................................................. 83
Hardware-Monitor-Specific Configuration Registers ........................................................................................................................... 90
System Management Bus-Specific Configuration Registers ................................................................................................................. 90
Power Management I/O-Space Registers .............................................................................................................................................. 91
System Management Bus I/O-Space Registers.................................................................................................................................... 100
Hardware Monitor I/O Space Registers .............................................................................................................................................. 103

Function 5 & 6 Registers - AC97 Audio & Modem Codecs ............................................................................................ 107

PCI Configuration Space Header Function 5 Audio ........................................................................................................................ 107
PCI Configuration Space Header Function 6 Modem...................................................................................................................... 108
Function 5 & 6 Codec-Specific Configuration Registers .................................................................................................................... 109
I/O Base 0 Registers Audio/Modem Scatter/Gather DMA................................................................................................................ 111
I/O Base 1 Registers Audio FM NMI Status Registers .................................................................................................................... 115
I/O Base 2 Registers MIDI / Game Port........................................................................................................................................... 115
Memory Mapped I/O APIC Registers (CG Silicon)............................................................................................................................ 116
Indexed I/O APIC 32-Bit Registers (CG Silicon) ............................................................................................................................... 116

FUNCTIONAL DESCRIPTIONS ................................................................................................................................................ 118

OWER

ANAGEMENT

.............................................................................................................................................................. 118

Power Management Subsystem Overview .......................................................................................................................................... 118
Processor Bus States ........................................................................................................................................................................... 118
System Suspend States and Power Plane Control ............................................................................................................................... 119
General Purpose I/O Ports................................................................................................................................................................... 119
Power Management Events ................................................................................................................................................................. 120
System and Processor Resume Events ................................................................................................................................................ 120
Legacy Power Management Timers .................................................................................................................................................... 121
System Primary and Secondary Events ............................................................................................................................................... 121
Peripheral Events ................................................................................................................................................................................ 121

ELECTRICAL SPECIFICATIONS ............................................................................................................................................. 122

BSOLUTE

AXIMUM

ATINGS

............................................................................................................................................... 122

DC C

HARACTERISTICS

.............................................................................................................................................................. 122

PACKAGE MECHANICAL SPECIFICATIONS ...................................................................................................................... 123

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