VT82885

Real Time Clock

VIA Technologies, Inc.

FEATURES

Drop-in replacement for IBM AT computer
clock/calendar.

Pin configuration closely matches the
DS12887, DS12885and DS12885Q

Counts seconds, minutes, hours, days,
day of the week, date, month, and year
with leap year compensation

Binary or BCD representation of time,
calendar and alarm

12- or 24-hour clock with AM and PM in
12-hour mode

Daylight Savings Time option

Intel bus timing

Multiplex bus for pin efficiency

Interfaced with software as 128 RAM
locations

- 14 bytes of clock and control registers
- 114 bytes of general purpose RAM

Programmable square wave output signal

Bus-compatible interrupt signals (IRQ#)

Three interrpts are separately software-
maskable and testable

- Times-of-day alarm once/second to

once/day

- Periodic rates from 122

s to 500 ms

- End of clock update cycle

Optional 28-pin PLCC surface mount
package

DESCRIPTION

The VT82885 Real Time Clock is designed
to be a direct replacement for the DS12885.
The VT82885 is identical in form, fit and
function to the DS12885. It has 114 bytes of
general purpose RAM. Access to this RAM
space is determined by the logic level
presented on AD6 during the address
portion of an access cycle. An external
crystal and battery are the only components
required to maintain time-of-day and
memory status in the absence of power. A
complete description of operating conditions,

electrical characteristics, bus timing and pin
descriptions follows.

PIN ASSIGNMENT

GND

AD0

AD1

SQW

RCLR#

BAT

IRQ#

RESET#

RD#

AD2

AD3

AD4

AD5

AD6

AD7

GND

WR#

CS#

VT82885 24 PIN DIP

AD0

AD1

AD2

AD3

AD4

AD5

RCLR#

BAT

IRQ#

RESET#

RD#

GND

WR#

X
2

X
1

G
N
D

N
C

S
Q
W

N
C

A
D
6

N
C

A
D
7

G
N
D

C
S
#

A
S

N
C

13 14 15 16 17

VT82885 28-PIN PLCC

PIN DESCRIPTION

AD0-AD7

- Multiplexed Address/Data Bus

- No Connection

CS#

- Chip Select

- Address Strobe

VT82885

Real Time Clock

VIA Technologies, Inc.

WR#

- Write Strobe

RD#

- Read Strobe

RESET#

- Reset Input

IRQ#

- Interrupt Request Output

SQW

- Square Wave Output

- +5 Volt Supply

GND

- Ground

X1, X2

- 32.768 kHz Crystal Connec-
tions

BAT

- +3 Volt Battery Input

RCLR#

- RAM Clear

OPERATION

The block diagram in Figure 1 shows the
pin connections with the major internal func-

tions of the VT82885. The following para-
graphs describe the function of each pin.

FIQURE 1: BLOCK DIAGRAM VT82885

POWER-DOWN/POWER-UP
CONSIDERATIONS

The Real Time Clock function will continue
to operate and all of the RAM, time, calen-
dar and alarm memory locations remain
nonvolatile regardless of the level of the V

input. When V

is applied to the VT82885

and reaches a level of greater than 4.25
volts, the device becomes ac-cessible after
100 ms, provided that the oscillator is
running and the oscillator countdown chain
is not in reset (see Register A). This time
period allows the system to stabilize after

OSC

+64

PERIODIC INTERUPT SQUARE WAVE

SELECTOR

SQUARE

WAVE OUT

POWER

SWITCH

AND

WRITE

PROTECT

BUS

INTERFACE

CLOCK/

CALENDAR

UPDATE

BCD/

BINARY

INCREMENT

REGISTERS A,B,C,D

CLOCK, CALENDAR

AND ALARM RAM

USER RAM

114 BYTES

GND

RD#

AD0-
AD7

WR#

BAT

CS#

SQW

IRQ#

RESET#

RCLR#

POK

VT82885

Real Time Clock

VIA Technologies, Inc.

power is applied. When V

falls below 4.25

volts, the chip select input is internally forced
to an inac-tive level regardless of the value
of CS# at the input pin. The VT82885 is,
therefore, write-protected. When V

falls

below the level of V

BAT

, the external V

supply is switched off and the external V

BAT

lithium energy source supplies power to the
Real Time Clock and the RAM memory.

SIGNAL DESCRIPTIONS

DC power is provided to the device on

thIs pin. V

is the +5 volt input. When 5

volts are applied within normal limits, the
device is fully accessible and data can be
written and read. When VCC is below 4.25
volts typical, reads and writes are inhibited.
However, the timekeeping function contin-
ues unaffected by the lower input voltage. As
VCC falls below V

BAT

, the RAM and

timekeeper are switched over to the exter-
nal lithium energy source. The timekeeping
function maintains an accuracy of

1 minute

per month at 25

C regardless of the voltage

input on the V

pin.

BAT

Battery input for any standard 3 volt

lithium cell or energy source. Battery vol-
tage must be held between 2.5 and 3.4 volts
for proper operation. A maximum load of .5

A at 25

C in the absence of V

power

should be used to size the external energy
source.

SQW (Square Wave Output)

The SQW

pin can output a signal from one of 13 taps
provided by the internal divider stages of the
Real Time Clock. The frequency of the SQW
pin can be changed by programming
Register A as shown in Table 1. The SQW
signal can be turned on and off using the
SQWE bit in Register B. The SQW signal is
not available when V

is less than 4.25

volts typical.

TABLE 1: PERIODIC INTERRUPT RATE AND SQUARE WAVE OUTPUT FREQUENCY

SELECT BITS REGISTER A

PERIODIC

SQW OUTPUT

RS3

RS2

RS1

RS0

INTERRUPT RATE

FREQUENCY

None

3.90625 ms

256 Hz

7.8125 ms

128 Hz

122.070

8.192 kHz

244.141

4.096 kHz

488.281

2.048 kHz

976.5625

1.024 kHz

1.953125 ms

512 Hz

3.90625 ms

256 Hz

7.8125 ms

128 Hz

15.625 ms

64 Hz

31.25 ms

32 Hz

62.5 ms

16 Hz

125 ms

8 Hz

250 ms

4 Hz

500 ms

2 Hz

VT82885

Real Time Clock

VIA Technologies, Inc.

X1, X2

These pins connect to a standard

32.768 kHz quartz crystal. The internal os-
cillator circuitry is designed for operation with
a crystal having a specified load capa-
citance (CL) of 6 pF. Each of the pins (X1
and X2) require the installation of an ex-
ternal 10 pF capacitor.

RCLR#

The RCLR# pin is used to clear

(set to logic 1) all 114 bytes of general pur-
pose RAM but does not affect the RAM as-
sociated with the real time clock. In order to
clear the RAM, RCLR# must be forced to an
input logic of 0 (-0.3 to +0.8 volts) during
battery back-up mode when V

is not ap-

plied. The RCLR# function is designed to be
used via human interface (shorting to ground
manually or by switch) and not to be driven
with external buffers. This pin is internally
pulled up.

AD0-AD7 (Multiplexed Bidirectional
Address/Data Bus)

Multiplexed buses

save pins because address information and
data information time share the same signal
paths. The addresses are present during the
first portion of the bus cycle and the same
pins and cycle paths are used for data in the
second portion of the cycle. Address/data
multiplexing does not slow the access time
of the VT82885 since the bus change from
address to data occurs during the internal
RAM access time. Addresses must be valid
prior to the falling edge of AS, at which time
the VT82885 latches the address from AD0
to AD6. Valid data must be present and held
stable during the latter portion of the RD# or
WR# pulses. In a read cycle the VT82885
outputs 8 bits of data during the latter portion
of the RD# or RD# pulses. The read cycle is
terminated and the bus returns to a high
impedence state as RD# transistions high as
in Intel timing.

AS (Adress Strobe Input)

A positive

going address strobe pulse serves to
demultiplex the bus. The falling edge of AS
causes the address to be latched within the
VT82885.

RD# (Read Strobe)

The RD# pin identifies

the time period when the VT82885 drives the
bus with read data. The RD# signal is the
same definition as the Output Enable (OE#)
signal on a typical memory.

WR# (Write Strobe)

The WR# pin is used

to indicate a write cycle.

CS# (Chip Select Input)

The Chip Select

signal must be asserted low for a bus cycle
in the VT82885 to be accessed. CS# must
be kept in the active state during RD# and
WR#. Bus cycles which take place without
asserting CS# will latch addresses but no
access will occur. When V

is below 4.25

volts, the VT82885 internally inhibits access
cycles by internally disabling the CS# input.
This action protects both the real time clock
data and RAM data during power outages.

IRQ# (Interrupt Request Output)

The

IRQ# pin is an active low output of the
VT82885 that can be used as an interrupt
input to a processor. The IRQ# output
remains low as long as the status bit causing
the interrupt is present and the
corresponding interrupt-enable bit is set. To
clear the IRQ# pin the processor program
normally reads the C register. The RESET#
pin also clears pending interrupts.

When no interrupt condition is present, the
IRQ# level is in the high impedence state.
Multiple interrupting devices can be
connected to an IRQ# bus. The IRQ# bus is
an open drain output and requires an
external pull-up resistor.

RESET# (Reset Input)

The RESET# pin

has no effect on the clock, calendar, or
RAM. On power-up the RESET# pin can be
held low for a time in order to allow the
power supply to stabilize. The amount of
time that RESET# is held low is dependent
on the application. However, if RESET# is
used on power-up, the time RESET# is low
should exceed 200 ms to make sure that the
internal timer that controls the VT82885 on
power-up has timed out. When RESET# is
low and V

is above 4.25 volts, the

following occurs:

A. Periodic Interrupt Enable (PEI) bit is

cleared to zero.

B. Alarm Interrupt Flag (AIE) bit is cleared

to zero.

C. Update Ended Interrupt Flag (UF) bit is

cleared to zero.

D. Interrupt Request Status Flag (IRQF) bit

is cleared to zero.

VT82885

Real Time Clock

VIA Technologies, Inc.

E. Periodic Interrupt Flag (PF) bit is cleared

to zero.

F. The device is not accessible until

RESET# is returned high.

G. Alarm Interrupt Flag (AF) bit is cleared to

zero.

H. IRQ# pin is in the high impedence state.

Square Wave Output Enable (SQWE)
bit is cleared to zero.

Update Ended Interrupt Enable (UIE) is
cleared to zero.

In a typical application RESET# can be
connected to V

. This connection will allow

the VT82885 to go in and out of power fail
without affecting any of the control registers.

ADDRESS MAP

The address map of the VT82885 is shown
in Figure 2. The address map consists of
114 bytes of user RAM, 10 bytes of RAM
that contain the RTC time, calendar and
alarm data, and four bytes which are used
for control and status. All 128 bytes can be
directly written or read except the following:

Registers C and D are read-only.

Bit 7 of Register A is read-only.

The high order bit of the seconds byte is
read-only.

The contents of four registers (A, B, C and
D) are described in the "Register" section.

FIGURE 2: ADDRESS MAP VT82885

TIME, CALENDAR AND ALARM
LOCATIONS

The time and calendar information is
obtained by reading the appropriate memory
bytes. The time, calendar and alarm are set

or initialized by writing the appropriate RAM
bytes. The contents of the ten time, calen-
dar and alarm bytes can be either Binary or
Binary-Coded Decimal (BCD) format. Be-
fore writing the internal time, calendar and
alarm registers, the SET bit in Register B

SECONDS

SECONDS ALARM

MINUTES

MINUTES ALARM

HOURS

HOURS ALARM

DAY OF THE WEEK

DAY OF THE MONTH

MONTH

YEAR

127

14 Bytes

Clock and Control

Status Registers

114 Bytes

Storage

Registers

Binary or BCD Input

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