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KT133 -

VT8363

Preliminary Revision 1.0, May 12, 2000

-1-

Features

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VIA VT8363

KT133 AMD A

THLON

TM N

ORTH

RIDGE

Single-Chip North Bridge

for Socket-A (Socket-462) Based Athlon CPUs

with 200 MHz Front Side Bus

for Desktop PC Systems

with AGP 4x and PCI

plus Advanced Memory Controller

supporting PC133 / PC100 SDRAM and VCM

�

High Performance and High Integration Athlon AGP 4x / PC133 Chipset with Advanced System
Power Management

KT133 Chipset: VT8363 system controller and VT82C686A PCI to ISA bridge

Single chip Athlon system controller with 64-bit Socket-A Athlon CPU, 64-bit system memory, 32-bit PCI and 32-
bit AGP interfaces

PCI-to-ISA bridge chip includes UltraDMA-33/66 EIDE, 4 USB Ports, Integrated Super-I/O, AC97 / MC97 link (for
Audio and Modem support), Hardware Monitoring, Power Management, and Keyboard / PS2-Mouse Interfaces plus
RTC / CMOS on chip

Supports separately powered 3.3V (5V tolerant) interface to system memory, AGP, and PCI bus

Modular power management and clock control for advanced system power management

�

High Performance Athlon CPU Interface

Supports Socket-A (Socket-462) AMD Athlon processors

HSTL-like 1.5V high-speed transceiver logic signal levels

Support independent address, data, and snoop interfaces

100 MHz DDR (Double Data Rate) transfer on Athlon CPU address and data buses

Built-in PLL (Phase Lock Loop) circuitry for optimal skew control within and between clocking regions

Four-entry command queue to accommodate maximum CPU throughput

Four-entry probe queue to stores probes from the system to the processor

Twenty four-entry processor system data and control queue to store system data control commands in two separate
read and write buffers for data movement in and out of processor interface

Supports WC (Write Combining) cycles

Sleep mode support

System management interrupt, memory remap and STPCLK mechanism

KT133 -

VT8363

Preliminary Revision 1.0, May 12, 2000

-2-

Features

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Full Featured Accelerated Graphics Port (AGP) Controller

Synchronous and pseudo-synchronous with the host CPU bus with optimal skew control

PCI

AGP

CPU

Mode

33 MHz

66 MHz

100 MHz DDR

3x synchronous

AGP v2.0 compliant

Supports SideBand Addressing (SBA) mode (non-multiplexed address / data)

Supports 66 MHz 1x, 2x and 4x modes for AD and SBA signaling

Pipelined split-transaction long-burst transfers up to 1GB/sec

Thirty-two level read request queue

Four level posted-write request queue

Thirty-two level (quadwords) read data FIFO (256 bytes)

Sixteen level (quadwords) write data FIFO (128 bytes)

Intelligent request reordering for maximum AGP bus utilization

Supports Flush/Fence commands

Graphics Address Relocation Table (GART)

One level TLB structure

Sixteen entry fully associative page table

LRU replacement scheme

Windows 95 OSR-2 VXD and integrated Windows 98 / Windows 2000 miniport driver support

�

Concurrent PCI Bus Controller

PCI buses are synchronous / pseudo-synchronous to host CPU bus

33 MHz operation on the primary PCI bus

66 MHz PCI operation on the AGP bus

PCI-to-PCI bridge configuration on the 66MHz PCI bus

Supports up to five PCI masters

Peer concurrency

Concurrent multiple PCI master transactions; i.e., allow PCI masters from both PCI buses active at the same time

Zero wait state PCI master and slave burst transfer rate

PCI to system memory data streaming up to 132Mbyte/sec

Two lines (32 double-words) of CPU to PCI posted write buffers

Byte merging in the write buffers to reduce the number of PCI cycles and to create further PCI bursting possibilities

Enhanced PCI command optimization (MRL, MRM, MWI, etc.)

Thirty-two levels (double-words) of post write buffers from PCI masters to DRAM
(two cache lines / 16 double-words for PCI bus, two cache lines / 16 double-words for Athlon processor interface)

Sixteen levels (double-words) of prefetch buffers from DRAM for access by PCI masters

Delay transaction from PCI master accessing DRAM

Read caching for PCI master reading DRAM

Transaction timer for fair arbitration between PCI masters (granularity of two PCI clocks)

Symmetric arbitration between Host/PCI bus for optimized system performance

Complete steerable PCI interrupts

PCI-2.2 compliant, 32 bit 3.3V PCI interface with 5V tolerant inputs

KT133 -

VT8363

Preliminary Revision 1.0, May 12, 2000

-3-

Features

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Advanced High-Performance DRAM Controller

Supports PC133 and PC100 SDRAM and Virtual Channel Memory (VCM) SDRAM up to 3 DIMMs

Concurrent CPU, AGP, and PCI access

Different DRAM types may be used in mixed combinations

Different DRAM timing for each bank

Dynamic Clock Enable (CKE) control for SDRAM power reduction in high speed systems

Mixed 1M / 2M / 4M / 8M / 16M / 32MxN DRAMs

Support up to 1.5 GB memory space (256Mb DRAM technology)

Flexible row and column addresses

64-bit data width and 3.3V DRAM interface

Programmable I/O drive capability for MA, command, and MD signals

Two-bank interleaving for 16Mbit SDRAM support

Two-bank and four bank interleaving for 64Mbit SDRAM support

Supports maximum 16-bank interleave (i.e., 16 pages open simultaneously); banks are allocated based on LRU

Independent SDRAM control for each bank

Seamless DRAM command scheduling for maximum DRAM bus utilization
(e.g., precharge other banks while accessing the current bank)

Four cache lines (32 quadwords) of CPU to DRAM write buffers

Four cache lines (32 quadwords) of CPU to DRAM read prefetch buffers

Read around write capability for non-stalled CPU read

Burst read and write operation

BIOS shadow at 16KB increment

Decoupled and burst DRAM refresh with staggered RAS timing

CAS before RAS or self refresh

�

Advanced System Power Management Support

Dynamic power down of SDRAM (CKE)

PCI and AGP bus clock run and clock generator control

VTT suspend power plane preserves memory data

Suspend-to-DRAM and Self-Refresh operation

SDRAM self-refresh power down

8 bytes of BIOS scratch registers

Low-leakage I/O pads

�

Built-in NAND-tree pin scan test capability

�

3.3V, 0.35um, high speed / low power CMOS process

�

35 x 35 mm, 552 pin BGA Package

协谢械泻褌褉芯薪薪褘泄 泻芯屑锌芯薪械薪褌: VT8363KT133AMDATHLONNORTHBRIDG

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: VT8363KT133AMDATHLONNORTHBRIDG