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VT8371
Preliminary Revision 1.02, January 7, 2000
-i-
Revision History
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EVISION
H
ISTORY
Document Release
Date
Revision
Initials
0.1
4/12/99
Initial internal release
DH
0.2
6/14/99
Updated feature bullets, overview and pin descriptions
Added ballout per engineering document revision 0.2
Added registers from 694X data sheet rev 0.61 (bank ending addresses fixed)
Updated package mechanical to 510 BGA
EC
DH
0.21
6/17/99
Fixed formatting problems on electrical specs page
DH
0.3
7/2/99
Updated feature bullets, overview, and block diagram
Updated pinouts (changed CPU interface and some DRAM data & AGP pins)
Updated package mechanical to BGA512
Updated register specs to reflect K7 register set (rev 0.2 was a copy of 694X)
DH
0.41
7/13/99
Fixed pinout errors in center VCC/GND and changed AGP & MD areas
Fixed strap options
Fixed device 0 registers Rx58-59, 61-63, 69, 7B, AC, AE, B4
Updated mechanical specs to 516 BGA
DH
0.5
7/20/99
Fixed typographical error in feature bullets regarding package pin count
Fixed formatting errors in page footer revision numbers and document date
Updated pinouts per engineering ballout rev 0.6: swapped PWROK & WSC#
Updated pinouts per engineering ballout rev 0.7: swapped D37# and VTT
Changed Device 0 and Device 1 Rx2 Device ID values
Fixed Device 0 Rx10[27-20] typographical error, Rx88[2] bit function, and
RxA0 and RxA4 default values (typographical errors)
DH
0.51
7/22/99
Fixed Device 0 Rx54[0] bit definition and Device 1 Rx2 Device ID
Added Device 0 RxC0-C7 Power Management registers
DH
0.6
8/26/99
Fixed GCKRUN# pin direction
Added strap to register cross references to MAA/MAB pin descriptions
Device 0
Fixed Rx3-2 (Device ID), 52[3], 68[0], 76[3-0], 7B[1], F0-F7
Fixed RxB4[3-2] strapping & RxB5[7,3] polarity; added RxB4-5 defaults
Device 1
Fixed Rx3-2 (Device ID), 1F-1E, Rx40[3], 42[4, 0], 44[4-1], 82[5], 83[2-1]
DH
1.0
11/1/99
Changed "K7" to Athlon" and reworded document title
Changed feature bullets in DRAM controller section
Removed "NDA Required" disclaimer (product announced)
Fixed minor typo in pinout table (pin lists and descriptions were correct)
Added Device 0 Rx55[1], moved Device 0 registers RxB4-B6 to B3-B5
DH
1.01
1/7/00
Removed "Socket-462" from description (chip is optimized for Slot-A)
Updated VIA Logo to "Delivering Value" format
DH
1.02
1/17/00
Fixed typos in DRAM controller feature bullets and Device 0 RxB2[0]
DH
VT8371
Preliminary Revision 1.02, January 7, 2000
-ii-
Table of Contents
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ABLE OF
C
ONTENTS
REVISION HISTORY........................................................................................................................................................................I
TABLE OF CONTENTS .................................................................................................................................................................. II
LIST OF FIGURES..........................................................................................................................................................................III
LIST OF TABLES ...........................................................................................................................................................................IV
KX133 AMD ATHLONTM NORTH BRIDGE................................................................................................................................. 1
OVERVIEW ....................................................................................................................................................................................... 4
PINOUTS ............................................................................................................................................................................................ 6
PIN DESCRIPTIONS ........................................................................................................................................................................ 9
REGISTERS ..................................................................................................................................................................................... 17
R
EGISTER
O
VERVIEW
................................................................................................................................................................. 17
M
ISCELLANEOUS
I/O................................................................................................................................................................... 20
C
ONFIGURATION
S
PACE
I/O ....................................................................................................................................................... 20
R
EGISTER
D
ESCRIPTIONS
............................................................................................................................................................ 21
Device 0 Header Registers - Host Bridge ............................................................................................................................ 21
Device 0 Configuration Registers - Host Bridge ................................................................................................................ 23
Host CPU Control ................................................................................................................................................................................. 23
DRAM Control ..................................................................................................................................................................................... 24
PCI Bus Control.................................................................................................................................................................................... 30
GART / Graphics Aperture Control ...................................................................................................................................................... 34
AGP Control ......................................................................................................................................................................................... 36
Device 1 Header Registers - PCI-to-PCI Bridge ................................................................................................................ 40
Device 1 Configuration Registers - PCI-to-PCI Bridge..................................................................................................... 42
AGP Bus Control .................................................................................................................................................................................. 42
ELECTRICAL SPECIFICATIONS ............................................................................................................................................... 45
A
BSOLUTE
M
AXIMUM
R
ATINGS
................................................................................................................................................. 45
DC C
HARACTERISTICS
................................................................................................................................................................ 45
AC T
IMING
S
PECIFICATIONS
...................................................................................................................................................... 45
MECHANICAL SPECIFICATIONS ............................................................................................................................................. 46
VT8371
Preliminary Revision 1.02, January 7, 2000
-iii-
List of Figures
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L
IST OF
F
IGURES
FIGURE 1. KX133 SYSTEM BLOCK DIAGRAM USING THE VT82C686A SOUTH BRIDGE .......................................... 4
FIGURE 2. VT8371 BALL DIAGRAM (TOP VIEW) .................................................................................................................. 6
FIGURE 3. VT8371 PIN LIST (NUMERICAL ORDER) ............................................................................................................. 7
FIGURE 4. VT8371 PIN LIST (ALPHABETICAL ORDER) ...................................................................................................... 8
FIGURE 5. CPU / SDRAM / AGP / PCI CLOCK CONNECTIONS ......................................................................................... 15
FIGURE 6. GRAPHICS APERTURE ADDRESS TRANSLATION ......................................................................................... 34
FIGURE 7. MECHANICAL SPECIFICATIONS - 516-PIN BALL GRID ARRAY PACKAGE ........................................... 46
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