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Электронный компонент: VT83C572

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VT83C572
PCI
TO
USB C
ONTROLLER
Preliminary Release 0.5
DATE : July 10, 1996
VIA TECHNOLOGIES, INC.
P
RELIMINARY
D
OCUMENT
R
ELEASE
The material in this document supersedes all previous documentation issued for any of the products
included herein. Please contact VIA Technologies for the latest documentation.
Copyright Notice:
Copyright
1995, 1996 Via Technologies Incorporated. Printed in Taiwan. A
LL
R
IGHTS
R
ESERVED
.
No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or
translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical,
chemical, manual or otherwise without the prior written permission of Via Technologies Incorporated.
Windows 95
TM
and Plug and Play
TM
are registered trademarks of Microsoft Corp.
PCI
TM
is a registered trademark of the PCI Special Interest Group.
All trademarks are the properties of their respective owners.
Disclaimer Notice:
No license is granted, implied or otherwise, under any patent or patent rights of VIA Technologies. VIA
Technologies makes no warranties, implied or otherwise, in regard to this document and to the products
described in this document. The information provided by this document is believed to be accurate and
reliable to the publication date of this document. However, VIA Technologies assumes no responsibility
for any errors in this document. Furthermore, VIA Technologies assumes no responsibility for the use or
misuse of the information in this document and for any patent infringements that may arise from the use
of this document. The information and product specifications within this document are subject to change
at any time, without notice and without obligation to notify any person of such change.
Offices:
5020 Brandin Court
8th Floor, No. 533
Fremont, CA
94538
Chung-Cheng Rd., Hsin-Tien
USA
Taipei, Taiwan ROC
Tel:
(510) 683-3300
Tel:
(886-2) 218-5452
Fax:
(510) 683-3301
Fax:
(886-2) 218-5453
VIA Technologies, Inc.
VT83C572
-1-
VIA VT83C572
PCI
TO
USB C
ONTROLLER
F
EATURES
* Universal Serial Bus Interface
-
USB specification v.1.0 compatible
-
Intel UHCI (Universal Host Controller Interface) v.1.1 register compatible
-
Legacy keyboard and PS2 mouse support
-
Root hub and two down stream function ports
-
Integrated physical layer transceivers
-
Normal and low power operating mode
-
Operable in both USB-aware (Windows-95 and NT) and USB legacy BIOS support
-
Inter-operable with major USB peripherals
* PCI Interface
-
PCI specification v.2.1 compliant
-
Supports advanced PCI commands
-
Multi-level data FIFOs with full scatter and gather capabilities
* 0.5um high speed low power CMOS process
* Single chip 100-pin PQFP device
VT83C572 C
ONFIGURATION
R
EGISTERS
The VT83C572 PCI to USB controller is fully compatible with the UHCI specification v.1.1. There
are two sets of software accessible registers -- PCI configuration registers and USB I/O registers. The
USB I/O registers are defined in the UHCI v.1.1 specification.
PCI Configuration Registers
Offset
Function
1-0
Vendor ID : 1106h
(read only)
3-2
Device ID : 3038h
(read only)
5-4
Command Register
bit 15-8: reserved
bit 7:
Address stepping, default: enabled
bit 6-5: reserved
VIA Technologies, Inc.
VT83C572
-2-
bit 4:
Memory write and invalidate, default: disabled
bit 3:
Fixed at 0 (special cycles)
bit 2:
Bus master, default: disabled
bit 1:
Memory space, default: disabled
bit 0:
I/O space, default: disabled
7-6
Status Register
bit 15:
reserved
bit 14:
Signaled system error
bit 13:
Received master abort
bit 12:
Received target abort
bit 11:
Signaled target abort
bit 10-9: DEVSEL# timing: fixed at 01 (medium)
bit 8-0: reserved
08
Revision ID.
B-9
Class Code Register:
Fixed at 0C0300h to indicate the USB Controller
0C
Cache Line Size
Default: 00h
0D
Latency Timer
Default: 16h
0E
Header Type = 00h
(read only)
0F
BIST
Fixed at 00
23-20
Base address for
UHCI v1.1 compliant USB IO Registers
bit 31-16:reserved
bit 15-5: Port address for the base USB IO Registers, corresponding to AD[15:5]
bit 4-0: 00001b
3C
Interrupt Line
3D
Interrupt Pin, Default = 01h
3E-3F
reserved
40
Misc. Control Register 1
bit 7:
PCI Memory Command Option
0 - Support Memory Read Line, Memory Read Multiple, Memory Write and Invalidate
1 - Only support Memory Read, Memory Write Commands
bit 6:
Babble Option
0 - Automatically disable babbled port when EOF babble occurs.
1 - Don't disable babbled port.
bit 5:
PCI Parity Check Option
0 - Disable PERR generation
1 - Enable parity check and PERR generation
bit 4:
reserved
bit 3:
USB Data Length Option
0 - Support TD length up to 1280.
1 - Support TD length up to 1023.
bit 2:
USB Power Management
VIA Technologies, Inc.
VT83C572
-3-
0 - Disable USB power management
1 - Enable USB power management
bit 1:
DMA Option
0 - 16DW burst access
1 - 8DW burst access
bit 0:
PCI Wait State
0 - Zero wait
1 - One wait
41
Misc. Control Register 2
bit7-3:
reserved
bit 2:
Trap Option
0 - Set trap 60/64 status bits without checking enable bits.
1 - Set trap 60/64 status bits only when trap 60/64 enable bits are set.
bit 1:
A20gate Pass Through Option
0 - Pass through A20GATE command sequence defined in UHCI.
1 - Don't pass through Write I/O port 64
bit 0:
reserved
42-5F
reserved
60
Serial Bus Release Number
fixed at 10h
C0-C1
Legacy Support Register (compliant with
UHCI v1.1 specification)
Default=2000h
USB I/O Registers (UHCI v1.1 Compliant)
Offset
Function
1-0
USB Command
3-2
USB Status
5-4
USB Interrupt Enable
7-6
Frame Number
B-8
Frame List Base Address
0C
Start Of Frame Modify
11-10
Port 1 Status/Control
13-12
Port 2 Status/Control