SPICE Device Model Si4921DY
Vishay Siliconix
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 72299
www.vishay.com
20-May-04
1
Dual P-Channel 30-V (D-S) MOSFET
CHARACTERISTICS
P-Channel Vertical DMOS
Macro Model (Subcircuit Model)
Level 3 MOS
Apply for both Linear and Switching Application
Accurate over the
-
55 to 125
C Temperature Range
Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the p-channel vertical DMOS. The subcircuit
model is extracted and optimized over the
-
55 to 125
C
temperature ranges under the pulsed 0 to 10V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched C
gd
model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
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SPICE Device Model Si4911DY
Vishay Siliconix
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Document Number: 72299
2
20-May-04
SPECIFICATIONS (T
J
= 25
C UNLESS OTHERWISE NOTED)
Parameter
Symbol
Test Conditions
Simulated
Data
Measured
Data
Unit
Static
Gate Threshold Voltage
V
GS(th)
V
DS
= V
GS
, I
D
=
-
250
A
2.1
V
On-State Drain Current
a
I
D(on)
V
DS
=
-
5 V, V
GS
=
-
10 V
234
A
V
GS
=
-
10 V, I
D
=
-
7.3 A
0.020
0.020
Drain-Source On-State Resistance
a
r
DS(on)
V
GS
=
-
4.5 V, I
D
=
-
5.6 A
0.035
0.033
Forward Transconductance
a
g
fs
V
DS
=
-
10 V, I
D
=
-
7.3 A
18
16
S
Diode Forward Voltage
a
V
SD
I
S
=
-
1.7 A, V
GS
= 0 V
-
0.80
-
0.80
V
Dynamic
b
Total Gate Charge
Q
g
32
33
Gate-Source Charge
Q
gs
5.8
5.8
Gate-Drain Charge
Q
gd
V
DS
=
-
15 V, V
GS
=
-
105 V, I
D
=
-
7.34 A
8.6
8.6
nC
Turn-On Delay Time
t
d(on)
20
10
Rise Time
t
r
15
15
Turn-Off Delay Time
t
d(off)
178
110
Fall Time
t
f
V
DD
=
-
15 V, R
L
= 15
I
D
-
1 A, V
GEN
=
-
10 V, R
G
= 6
34
70
Source-Drain Reverse Recovery Time
t
rr
I
F
=
-
1.7 A, di/dt 100 A/
s
55
60
ns
Notes
a. Pulse test; pulse width
300
s, duty cycle
2%.
b. Guaranteed by design, not subject to production testing.
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SPICE Device Model Si4921DY
Vishay Siliconix
Document Number: 72299
www.vishay.com
20-May-04
3
COMPARISON OF MODEL WITH MEASURED DATA (T
J
=25
C UNLESS OTHERWISE NOTED)
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