SPICE Device Model Si1404DH
Vishay Siliconix
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 73120
www.vishay.com
27-Aug-04
1
N-Channel 25-V (D-S) MOSFET
CHARACTERISTICS
N-Channel Vertical DMOS
Macro Model (Subcircuit Model)
Level 3 MOS
Apply for both Linear and Switching Application
Accurate over the -55 to 125C Temperature Range
Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the
-55 to 125C
temperature ranges under the pulsed 0 to 5V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched C
gd
model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
SPICE Device Model Si1404DH
Vishay Siliconix
www.vishay.com
Document Number: 73120
2
27-Aug-04
SPECIFICATIONS (T
J
= 25
C UNLESS OTHERWISE NOTED)
Parameter Symbol
Test
Conditions
Simulated
Data
Measured
Data
Unit
Static
Gate Threshold Voltage
V
GS(th)
V
DS
= V
GS
, I
D
= 250
A
1 V
On-State Drain Current
a
I
D(on)
V
DS
= 5 V, V
GS
= 4.5 V
11
A
V
GS
= 4.5 V, I
D
= 1.57 A
0.28
0.28
Drain-Source On-State Resistance
a
r
DS(on)
V
GS
= 2.5 V, I
D
= 1.39 A
0.33
0.36
Forward Transconductance
a
g
fs
V
DS
= 15 V, I
D
= 0.75 A
2.3
1.5
S
Diode Forward Voltage
a
V
SD
I
S
= 1.23 A, V
GS
= 0 V
0.76
0.85
V
Dynamic
b
Total Gate Charge
Q
g
1
1.3
Gate-Source Charge
Q
gs
0.31
0.31
Gate-Drain Charge
Q
gd
V
DS
= 15 V, V
GS
= 4.5 V, I
D
= 1.57 A
0.49 0.49
nC
Turn-On Delay Time
t
d(on)
12
11
Rise Time
t
r
15
18
Turn-Off Delay Time
t
d(off)
19
17
Fall Time
t
f
V
DD
= 15 V, R
L
= 20
I
D
0.75 A, V
GEN
= 4.5 V, R
G
= 6
21 11
ns
Notes
a. Pulse test; pulse width
300 s, duty cycle 2%.
b. Guaranteed by design, not subject to production testing.
SPICE Device Model Si1404DH
Vishay Siliconix
Document Number: 73120
www.vishay.com
27-Aug-04
3
COMPARISON OF MODEL WITH MEASURED DATA (T
J
=25
C UNLESS OTHERWISE NOTED)
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