VITESSE
SEMICONDUCTOR CORPORATION
Page 1
3/4/99
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
VSC7126
1.0625 Gbits/sec Fibre
Channel Transceiver
G52148-0, Rev. 4.3
Features
General Description
The VSC7126 is a full-speed Fibre Channel Transceiver optimized for Host Adapter and other space- con-
strained applications. It accepts two 10-bit 8B/10B encoded transmit characters, latches them on the rising edge
of TBC and serializes the data onto the TX+/- PECL differential outputs at a baud rate which is twenty times the
TBC frequency. It also samples serial receive data on the RX+/- PECL differential inputs, recovers the clock
and data, deserializes it onto two 10-bit receive characters, outputs a recovered clocks at one twentieth of the
incoming baud rate and detects Fibre Channel "Comma" characters. The VSC7126 contains on-chip PLL cir-
cuitry for synthesis of the baud-rate transmit clock, and extraction of the clock from the received serial stream.
These circuits are fully monolithic and require no external components.
VSC7126 Block Diagram
ANSI X3T11 Fibre Channel Compatible 1.0625
Gbps Full-duplex Transceiver
GLM Compatible (FCSI-301-Rev 1.0)
20 Bit TTL Interface For Transmit And Receive Data
Monolithic Clock Synthesis And Clock Recovery -
No External Components
53.125 MHz TTL Reference Clock
Automatic Lock-to-Reference Function
Suitable For Both Copper And Fiber
Optical Link Applications
Low Power Operation - 850 mW
80 Pin, 14x14 mm PQFP
Single +3.3V Power Supply
RX+
RX-
Q D
Serial to
Parallel
Clock
Recovery
Retimed
Data
Recovered
Comma
Detect
Q D
R0:19
Frame
Logic
COM_DET
EN_CDET
T0:19
PLL Clock
Multiply (x20)
D Q
Parallel
to Serial
Serial Data
Clock
Synthesized
Clock
D Q
TX+
TX-
EWRAP
20
RBC(0)
20
20
TBC
2:1
RBC(1)
TXEN#
L_UNUSE
53.125 MHz
53.125 MHz
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
VSC7126
1.0625 Gbits/sec Fibre
Channel Transceiver
Page 2
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
3/4/99
G52148-0, Rev. 4.3
Functional Description
Clock Synthesizer:
The VSC7126 clock synthesizer multiplies the 53.125 MHz reference frequency provided on the TBC pin
by 20 to achieve a baud rate clock at nominally 1.0625 GHz. The clock synthesizer contains a fully monolithic
PLL which does not require any external components.
Serializer:
The VSC7126 accepts TTL input data as two parallel 10 bit characters on the T0:19 bus which is latched
into the input latch on the rising edge of TBC. This data will be serialized and transmitted on the TX PECL dif-
ferential outputs at a baud rate of twenty times the frequency of the TBC input, with bit T0 transmitted first.
User data should be encoded for transmission using the 8B/10B block code described in the Fibre Channel spec-
ification, or an equivalent, edge rich, DC-balanced code. If either EWRAP or TXEN# is HIGH the transmitter
will be disabled with TX+ HIGH and TX- LOW. If both EWRAP and TXEN# are LOW, the transmitter outputs
serialized data.
Transmission Character Interface
In Fibre Channel, an encoded byte is 10 bits and is referred to as a transmission character. The 20 bit inter-
face on the VSC7126 corresponds to two transmission characters. This mapping is illustrated in Figure 1.
Figure 1: Transmission Order and Mapping to Fibre Channel Character
Clock Recovery:
The VSC7126 accepts differential high speed serial inputs on the RX+/RX- pins, (when EWRAP is LOW),
extracts the clock and retimes the data. The serial bit stream should be encoded to provide DC balance and lim-
ited run length by a Fibre Channel compatible 8B/10B transmitter or equivalent. The VSC7126 clock recovery
circuitry is completely monolithic and requires no external components. For proper operation, the baud rate of
the data stream to be recovered should be within 200 ppm of twenty times the TBC frequency. This allows
oscillators on either end of the link to be 53.125 MHz +/- 100ppm.
Deserializer:
The retimed serial bit stream is converted into two 10-bit parallel output characters. The VSC7126 provides
a TTL recovered clock, RBC(0) and its complement RBC(1), at one-twentieth of the serial baud rate. The
clocks are generated by dividing down the high-speed clock which is phase locked to the serial data. The serial
data is retimed by the internal high-speed clock, and deserialized. The resulting parallel data will be captured
Parallel Data Bits
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
8B/10B Bit Position
j
h
g
f
i
e
d
c
b
a
j
h
g
f
i
e
d
c
b
a
Valid Comma Position
1
1
1
1
1
0
0
First Data Bit Transmitted
Last Data Bit Transmitted
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SEMICONDUCTOR CORPORATION
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741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
VSC7126
1.0625 Gbits/sec Fibre
Channel Transceiver
G52148-0, Rev. 4.3
by the adjoining protocol logic on the falling edge of RBC(0). In order to maximize the setup and hold times
available at this interface, the parallel data is loaded into the output register at a point nominally midway
between the falling edges of RBC(0).
If serial input data is not present, or does not meet the required baud rate, the VSC7126 will continue to
produce a recovered clock so that downstream logic may continue to function. In the absence of a signal, the
RBC(0)/RBC(1) output clocks will immediately lock to the TBC reference clock.
Word Alignment:
The VSC7126 provides 7-bit Fibre Channel comma character recognition and data word alignment. Word
synchronization is enabled by asserting EN_CDET HIGH. When synchronization is enabled, the VSC7126
constantly examines the serial data for the presence of the Fibre Channel "comma" character. This pattern is
"0011111XXX", where the leading zero corresponds to the first bit received. The comma sequence is not con-
tained in any normal 8B/10B coded data character or pair of adjacent characters. It occurs only within special
characters, known as K28.1, K28.5 and K28.7, which are defined specifically for synchronization in Fibre
Channel systems. Improper alignment of the comma character is defined as any of the following conditions:
1) The comma is not aligned within the 10-bit transmission character such that T0...T6 = "0011111"
2) The comma straddles the boundary between two 10-bit transmission characters.
When EN_CDET is HIGH and an improperly aligned comma is encountered, the internal data is shifted in
such a manner that the comma character is aligned properly in R0:6 as shown in Figure 1. This results in proper
character and word alignment. When the parallel data alignment changes in response to an improperly aligned
comma pattern, some data which would have been presented on the parallel output port may be lost. However,
the synchronization character and subsequent data will be output correctly and properly aligned. When
EN_CDET is LOW, the current alignment of the serial data is maintained indefinitely, regardless of data pattern.
On encountering a comma character, COM_DET is driven HIGH to inform the user that realignment of the
parallel data field may have occurred. The COM_DET pulse is presented simultaneously with the comma char-
acter and has a duration equal to the data. The COM_DET signal is timed such that it can be captured by the
adjoining protocol logic on the falling edge of RBC(0). Functional waveforms for synchronization are given in
Figure 2 and Figure 3. Figure 2 shows the case when a comma character is detected and no phase adjustment is
necessary. It illustrates the position of the COM_DET pulse in relation to the comma character on R0:6.
Figure 3 shows the case where the K28.5 is detected, but it is out of phase and a change in the output data align-
ment is required. Note that up to three characters prior to the comma character may be corrupted by the realign-
ment process.
Signal Detection:
An output, LUNUSE, is provided to signal when the link is open or down. This signal is asserted if R0:19
are all either LOW or HIGH and EWRAP is LOW.
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
VSC7126
1.0625 Gbits/sec Fibre
Channel Transceiver
Page 4
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
3/4/99
G52148-0, Rev. 4.3
Figure 2: Detection of a Properly Aligned Comma Character
Figure 3: Detection and Resynchronization of an Improperly Aligned Comma
TChar: 10 bit Transmission Character
COM_DET
R0:9
K28.5 TChar TChar TChar
R10:19
TChar TChar TChar TChar
RBC(0)
COM_DET
Receiving Two Consecutive K28.5+TChar Transmission Words
K28.5 TChar TChar TChar
K28.5
TChar
PC = Potentially Corrupted
R0:9
TChar TChar TChar TChar
TChar
TChar
R10:19
PC
PC
PC
RBC(0)
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SEMICONDUCTOR CORPORATION
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741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
VSC7126
1.0625 Gbits/sec Fibre
Channel Transceiver
G52148-0, Rev. 4.3
AC Characteristics
Figure 4: Transmit Timing Waveforms
Table 1: Transmit AC Characteristics
Parameters
Description
Min
Max
Units
Conditions
T
1
T0:19 Setup time to the
rising edge of TBC
1.5
--
ns.
Measured between the valid data level of
T0:19 to the 1.4V point of TBC
T
2
T0:19 hold time after the
rising edge of TBC
2.5
--
ns.
T
SDR
,T
SDF
TX+/TX- rise and fall time
--
300
ps.
20% to 80%, 75 Ohm load to Vdd-2V
Tested on a sample basis
T
LAT
Latency from rising edge
of TBC to T0 appearing on
TX+/TX-
20 bc - 4 ns
ns.
bc = Bit Clock Periods
Transmitter Output Jitter Allocation
T
RJ
Serial data output random
jitter (RMS)
--
20
ps.
RMS, tested on a sample basis
(refer to Figure 8)
T
DJ
Serial data output
deterministic jitter (p-p)
--
120
ps.
Peak to peak, tested on a sample basis
(refer to Figure 8)
Data Valid
T0:19
T
1
20 Bit Data
T
2
TBC
Data Valid
Data Valid
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SEMICONDUCTOR CORPORATION
Datasheet
VSC7126
1.0625 Gbits/sec Fibre
Channel Transceiver
Page 6
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
3/4/99
G52148-0, Rev. 4.3
Figure 5: Receive Timing Waveforms
Table 2: Receive AC Characteristics
Parameters
Description
Min.
Max.
Units
Conditions
T
1
Data or COM_DET Valid
prior to RBC(0) fall
4
--
ns.
Measured between the 1.4V
point of RBC(0) and a valid
level of R0:19 or
COM_DET. All outputs
driving 10pF load.
T
2
Data or COM_DET Valid
after RBC(0) fall
6.0
--
ns.
T
4
Deviation of RBC(0) falling
edge to falling edge delay
from nominal.
-500
500
ps.
Nominal delay is 20 bit
times.
Tested on sample basis
T
R
, T
F
R0:19, COM_DET, RBC(0)
rise and fall time
0.7
2.4
ns.
Between V
il(max)
and
V
ih(min)
, into 10 pf. load.
R
lat
Latency from RX to RBC(0)
falling and RO valid.
40 bc + 10 ns
59 bc + 10 ns
Bit
Clocks
bc = bit clock periods
T
SKEW
Skew between edges of
RBC(0) and RBC(1)
----
1.5
ns
T
LOCK
Data acquisition lock time @
1.0625Gb/s
--
2.4
s.
8B/10B IDLE pattern.
Tested on a sample basis
RBC(0)
R0:19 &
T
2
Data Valid
Data Valid
T
1
T
3
Data Valid
COM_DET
LUNUSE
RBC(1)
T
SKEW
NOTE: Probability of Recovery for data acquisition is 95% per section 5.3 of the FC-PH rev 4.3.
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SEMICONDUCTOR CORPORATION
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3/4/99
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
VSC7126
1.0625 Gbits/sec Fibre
Channel Transceiver
G52148-0, Rev. 4.3
Figure 6: TBC Timing Waveforms
Table 3: Reference Clock Requirements
Parameters
Description
Min
Max
Units
Conditions
FR
Frequency Range
50
55
MHz
Range over which both transmit and receive
reference clocks on any link may be centered
FO
Frequency
Offset -200
200
ppm.
Mean frequency offset between transmit and
receive reference clocks on one link
T
L
,T
H
Pulse Width, Low / High
4.5
----
ns
Low is measured from V
il
(max) to V
il
(max),
High is measured from V
ih
(min) to V
ih
(min)
DC
TBC duty cycle
30
70
%
Measured at 1.5V
T
RCR
,T
RCF
TBC rise and fall time
----
2.0
ns.
Between V
il(max)
and V
ih(min)
J
T
Total jitter tolerance on
REFCLK
----
120
ps
Peak-to-peak total jitter for frequencies
between 50KHz and 7MHz
TBC
V
il(max)
V
ih(min)
T
L
T
H
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
VSC7126
1.0625 Gbits/sec Fibre
Channel Transceiver
Page 8
VITESSE
SEMICONDUCTOR CORPORATION
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3/4/99
G52148-0, Rev. 4.3
DC Characteristics
(Over recommended operating conditions).
Absolute Maximum Ratings
(1)
Power Supply Voltage, (V
DD
) ............................................................................................................-0.5V to +4V
DC Input Voltage (PECL inputs)............................................................................................ -0.5V to V
DD
+0.5V
DC Input Voltage (TTL inputs) ......................................................................................................... -0.5V to 5.5V
DC Output Voltage (TTL Outputs)........................................................................................ -0.5V to V
DD
+ 0.5V
Output Current (TTL Outputs) ................................................................................................................. +/-50mA
Output Current (PECL Outputs)................................................................................................................+/-50mA
Case Temperature Under Bias .........................................................................................................-55
o
to +125
o
C
Storage Temperature..................................................................................................................... -65
o
C to +150
o
C
Maximum Input ESD (Human Body Model) ............................................................................................... 1500V
Recommended Operating Conditions
Power Supply Voltage, (V
DD
) ................................................................................................................+3.3V+5%
Operating Temperature Range ................................................................0
o
C Ambient to 90
o
C Case Temperature
Notes:
(1)
CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing
permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended
periods may affect device reliability.
Parameters
Description
Min
Typ
Max
Units
Conditions
V
OH
Output HIGH voltage (TTL)
2.4
2.9
--
V
I
OH
= -1.0 mA
V
OL
Output LOW voltage (TTL)
--
--
0.5
V
I
OL
= +1.0 mA
V
OUT75
Serial Output voltage
differential peak-to-peak swing
(TX+/TX-)
1200
--
2200
mV
75
to V
DD
2.0 V
V
OUT50
Serial Output voltage
differential peak-to-peak swing
(TX+/TX-)
1000
--
2200
mV
50
to V
DD
2.0 V
V
IN
Serial Input voltage differential
peak-to-peak swing (RX+/RX-)
400
--
3200
mV
V
IH
Input HIGH voltage (TTL)
2.0
--
5.5
V
V
IL
Input LOW voltage (TTL)
0
--
0.8
V
--
I
IH
Input HIGH current (TTL)
--
50
500
A
V
IN
= 2.4 V
I
IL
Input LOW current (TTL)
--
--
-500
A
V
IN
= 0.5 V
V
DD
Supply voltage
3.14
--
3.47
V
3.3V5%
P
D
Power dissipation
--
850
1560
mW
Outputs open,
V
DD
=
V
DD
max
I
DD
Supply Current
--
245
450
mA
Outputs open,
V
DD
=
V
DD
max
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SEMICONDUCTOR CORPORATION
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741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
VSC7126
1.0625 Gbits/sec Fibre
Channel Transceiver
G52148-0, Rev. 4.3
Figure 7: Parametric Measurement Information
Serial Input Rise and Fall Time
TTL Input and Output Rise and Fall Time
TTL A.C. Output Load
Receiver Input Eye Diagram Jitter Tolerance Mask
Serial Output Load
T
r
T
f
80%
20%
T
r
T
f
V
ih(min)
V
il(max)
10 pF
Z
0
= 75
75
V
DD
2.0V
Bit Time
Eye Width%
Amplitude
Parametric Test Load Circuit
Total jitter tolerance is
0.7UI, according to
Fibre Channel 4.3 Annex J
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
VSC7126
1.0625 Gbits/sec Fibre
Channel Transceiver
Page 10
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
3/4/99
G52148-0, Rev. 4.3
Figure 8: Transmitter Jitter Measurement Method
BERT
Pattern
Generator
DATA
DATA
Digitizing
Scope
Trigger
VSC7126
TX
TBC
T00:19
-K28.7 -K28.7
0011111000 0011111000
TX+
TX-
1.0625 Gbit/s
53.125MHz
Random jitter (RJ) measurements performed according to Fibre Channel 4.3 Annex A, Test Methods, Section
A.4.4. Measure standard deviation of all 50% crossing points. Peak to peak RJ is + 7 sigma of distribution.
CLK = 1.0625 GHz
-K28.5 +K28.5
0011111010 1100000101
RJ
DJ
Single-Ended Measurement
Random Jitter Measurement
53.125MHz
BERT
Pattern
Generator
DATA
PAT SYNC
Digitizing
Scope
Trigger
VSC7126
TX
TBC
T0:19
TX+
TX-
1.0625 Gbit/s
53.125
CLK = 1.0625 GHz
Single-Ended Measurement
DATA = 00000 0000011111 11111
53.125MHz
Deterministic jitter (DJ) mea-
surements performed according to
Fibre Channel 4.3 Annex A, Test
Methods, Section A.4.3. Measure
time of all the 50% points of all ten
transitions. DJ is the range of the
timing variation from expected.
2 bit time
7 bit time
8 bit time
DATA
TRIGGER
9 bit time
10 bit time
12 bit time
17 bit time
18 bit time
19 bit time
20 bit time
Deterministic Jitter Measurement
DATA = 00000 0000011111 11111
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SEMICONDUCTOR CORPORATION
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VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
VSC7126
1.0625 Gbits/sec Fibre
Channel Transceiver
G52148-0, Rev. 4.3
Input Structures
Figure 9: Input Structures
INPUT
INPUT
High Speed Differential Input
V
DD
GND
+3.3 V
(RX+/RX-)
A
B
TBC and TTL Inputs
INPUT
+3.3 V
Current
Limit
GND
V
DD
R
R
All Resistors
3.3K
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
VSC7126
1.0625 Gbits/sec Fibre
Channel Transceiver
Page 12
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
3/4/99
G52148-0, Rev. 4.3
Package Pin Descriptions
Figure 10: Pin Diagram
Table 4: Pin Identification
Pin #
Name
Description
2,4,6,9,11,14,
16,18,20,23,3,
5,8,10,12,15,
17,19,22,24
T0:19
Transmit Data Bus, Bits 0 thru 19. INPUTS - TTL
20-bit transmit character. Parallel data on this bus is clocked in on the rising edge of
TBC. The data bit corresponding to T0 is transmitted first.
31
TBC
Transmit Byte Clock. INPUT - TTL
This rising edge of this clock latches T0:9 into the input register. It also provides the
reference clock, at one twentieth of the baud rate to the PLL.
79
77
TX+
TX-
Transmitter Serial Outputs. OUTPUTS - Differential PECL
These pins output the serialized transmit data when EWRAP is LOW. When EWRAP is
HIGH, TX+ is HIGH and TX- is LOW. (AC Coupling recommended)
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SEMICONDUCTOR CORPORATION
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VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
VSC7126
1.0625 Gbits/sec Fibre
Channel Transceiver
G52148-0, Rev. 4.3
65,63,59,57,
55,52,50,48,
45,43,64,62,
58,56,54,51,
49,47,44,42
R0:19
Receive Data Bus, Bits 0 thru 19 OUTPUTS - TTL
20-bit received character. Parallel data on this bus is clocked out on the rising edge of
RBC(0). R0 is the first bit received on RX+/RX-.
34
EWRAP
Enable Internal WRAP Mode. INPUT - TTL
LOW for Normal Operation. When HIGH, an internal loopback path from the
transmitter to the receiver is enabled, TX+ = HIGH and TX- is LOW.
70
69
RX+
RX-
Receive Serial Inputs INPUTS - Differential PECL
The receiver inputs when EWRAP is LOW. Internally biased to VDD/2, with 3.3K
resistors to VDD and GND. (AC Coupling recommended)
39
38
RBC(0)
RBC(1)
Recovered Byte Clock and Complement OUTPUT - TTL
Recovered clock and complement derived from one twentieth of the RX+/- data stream.
The rising edge of RBC(0) corresponds to a new word on R0:19.
27
EN_CDET
ENable Comma DETect. INPUT - TTL
Enables comma detection and word resynchronization when HIGH. When LOW, keeps
current word alignment and disables comma detection.
37
COMDET
COMma DETect OUTPUT - TTL
This output goes HIGH to indicate that R0:6 contains a Comma Character (`0011111').
COMDET will go HIGH only during a cycle when RBC(0) is falling. COMDET is
enabled by EN_CDET being HIGH.
35
TXEN#
Transmitter ENable INPUT - TTL
When LOW, the TX outputs transmit serial data. When HIGH, the TX+ is HIGH and the
TX- is LOW.
66
LUNUSE
Link UNUSE OUTPUT - TTL
Normally is LOW. If R0:19 is all LOW or all HIGH and EWRAP is LOW, this output
will be asserted HIGH to indicate an open link on RX+/-.
26
28
29
TEST1
TEST2
TEST3
TEST Mode Pins INPUT - TTL
Factory test pins. Tie to VDD for normal operation.
1,21,30,68,72
VSS
Digital Ground
40,41,60,61
VSST
Digital Ground for TTL Outputs
74
VSSA
Analog Ground
7,13,25,32,33,
67,71,75
VDD
Digital Power (3.3V)
36,46,53
VDDT
Digital Power for TTL outputs (3.3V)
76,80
VDDP
Digital Power for PECL outputs (3.3V)
73
VDDA
Analog Power (3.3V)
78
N/C
Not Internally Connected.
Pin #
Name
Description
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SEMICONDUCTOR CORPORATION
Datasheet
VSC7126
1.0625 Gbits/sec Fibre
Channel Transceiver
Page 14
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SEMICONDUCTOR CORPORATION
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3/4/99
G52148-0, Rev. 4.3
Package Information
10
TYP
10
TYP
A
D
K
G
F
I
H
60
41
80
61
1
20
21
40
0.30 RAD. TYP
.
0.20 RAD. TYP.
A
0.25 MAX.
E
J
0.25
0.17 MAX.
0 - 8
STANDOFF
COPLANARITY
0.102 MAX LEAD
Item
14 mm
Tolerance
A
2.35
MAX
D
2.00
+0.10/-0.05
E
0.30
.05
F
17.20
.25
G
14.00
.10
H
17.20
.25
I
14.00
.10
J
0.88
+.15/-.10
K
0.65
BASIC
NOTES:
Drawing not to scale.
All units in mm unless otherwise noted.
80-pin PQFP Package Drawing
VITESSE
SEMICONDUCTOR CORPORATION
Page 15
3/4/99
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
VSC7126
1.0625 Gbits/sec Fibre
Channel Transceiver
G52148-0, Rev. 4.3
Package Thermal Characteristics
The VSC7126 is packaged in a 14 mm PQFP with an integrated heat spreader. These packages use indus-
try-standard EIAJ footprints, but have been enhanced to improve thermal dissipation. The construction of the
packages is as shown in Figure 11.
Figure 11: Package Cross Section - 14 mm package
Table 5: Thermal Resistance
The VSC7126 is designed to operate with a case temperature up to 90
o
C. The user must guarantee that the
temperature specification is not violated. With the Thermal Resistances shown above, the 14x14 PQFP can
operate in still air ambient temperatures of 40
o
C (40C = 90C - 1.56W * 32C/W). If the ambient air tempera-
ture exceeds these limits, then some form of cooling through a heatsink or an increase in airflow will be needed.
Moisture Sensitivity Level
This device is rated with a moisture sensitivity level 3 rating. Refer to Application Note AN-20 for appro-
priate handling procedures.
Symbol
Description
14mm Value
Units
jc
Thermal resistance from junction to case
17
o
C/W
ca
Thermal resistance from case to ambient in still air including
conduction through the leads.
32
o
C/W
ca-100
Thermal resistance from case to ambient with 100 LFM airflow
28
o
C/W
ca-200
Thermal resistance from case to ambient with200 LFM airflow
25
o
C/W
ca-400
Thermal resistance from case to ambient with 400 LFM airflow
22
o
C/W
ca-600
Thermal resistance from case to ambient with 600 LFM airflow
20
o
C/W
Copper Heat Spreader
Die
Plastic Molding Compound
Lead
Bond Wire
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
VSC7126
1.0625 Gbits/sec Fibre
Channel Transceiver
Page 16
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
3/4/99
G52148-0, Rev. 4.3
Ordering Information
The order number for this product is formed by a combination of the device number, and package type.
Notice
Vitesse Semiconductor Corporation reserves the right to make changes in its products, specifications or
other information at any time without prior notice. Therefore the reader is cautioned to confirmation that this
datasheet is current prior to placing any orders. The company assumes no responsibility for any circuitry
described other than circuitry entirely embodied in a Vitesse product.
Warning
Vitesse Semiconductor Corporation's product are not intended for use in life support appliances, devices or systems.
Use of a Vitesse product in such applications without written consent is prohibited.
VSC7126
QX
Device Type
VSC7126: 1.0625 Gbps Transceiver
Package Style
QX: 80-pin, 14 x 14 mm PQFP
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