VITESSE

SEMICONDUCTOR CORPORATION

Page 1

1/17/00

741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

10-bit Transceiver for Fibre

Channel and Gigabit Ethernet

Advance Product Information

VSC7133

G52187-0 Rev. 2.4

Features

General Description

The VSC7133 is a full-speed Fibre Channel and Gigabit Ethernet Transceiver with industry-standard

pinouts. It accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of the TTL/PECL REF-
CLK and serializes it onto the TX PECL differential outputs at a baud rate which is ten times the REFCLK fre-
quency. Serial data input on the RX PECL differential inputs is resampled by the Clock Recovery Unit,
deserialized onto the 10-bit receive data bus synchronously to complementary divide-by-twenty clocks. The
VSC7133 receiver detects "Comma" characters for frame alignment. An analog/digital signal detection circuit
indicates that a valid signal is present on the RX input. A cable equalizer compensates for Inter Symbol Interfer-
ence in order to increase maximum cable distances. The VSC7133 contains PLL circuitry for synthesis of the
baud-rate transmit clock, and extraction of the clock from the received serial stream. The VSC7133 is similar to
the VSC7123 but has either a TTL or a PECL reference clock.

VSC7133 Block Diagram

· 802.3z Gigabit Ethernet Compliant 1.25

Gb/s Transceiver

· ANSI X3T11 Fibre Channel Compliant

1.0625 Gb/s Transceiver

· 0.98 to 1.36 Gb/s Full Duplex Operation

· 10 Bit TTL Interface for Transmit and

Receive Data

· TTL or PECL Reference Clock

· Automatic Lock-to-Reference

· RX Cable Equalization and Signal Detect

· JTAG Access Port for Testability

· 64-pin, 10mm PQFP Packaging

· Single +3.3V Supply, 650 mW

RX+

RX-

Q D

Serial to

Parallel

Clock

Recovery

Comma

R(0:9)

COMDET

ENCDET

T(0:9)

x10 Clock

Multiply

Parallel

to Serial

TX+

TX-

EWRAP

RCLK

2:1

RCLKN

Signal
Detect

Q D

Detect

SIGDET

D Q

NOT SHOWN: JTAG Boundary Scan

REFCLKP

REFCLKN

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC7133

10-bit Transceiver for Fibre

Channel and Gigabit Ethernet

Page 2

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896

1/17/00

G52187-0 Rev. 2.4

Functional Description

Clock Synthesizer

The VSC7133 clock synthesizer multiplies the reference frequency provided on the REFCLK pin by 10 to

achieve a baud rate clock between 0.98 and 1.36 GHz. The on-chip PLL uses a single external 0.1uF capacitor
to control the Loop Filter. The REFCLK is either TTL or LV PECL. If TTL, connect the TTL input to
REFLKP and leave REFCLKN open, it is biased for a TTL switch level. If PECL, connect both REFCLKP and
REFCLKN.

Serializer

The VSC7133 accepts TTL input data as a parallel 10 bit character on the T(0:9) bus, which is latched into

the input register on the rising edge of REFCLK. This data is serialized and transmitted on the TX PECL differ-
ential outputs at a baud rate that is ten times the frequency of the REFCLK, with bit T0 transmitted first. User
data should be encoded using 8B/10B block code or equivalent.

Transmission Character Interface

An encoded byte is 10 bits and is referred to as a transmission character. The 10 bit interface on the

VSC7133 corresponds to a transmission character. This mapping is illustrated in Figure 1.

Figure 1: Transmission Order and Mapping of an 8B/10B Character

Clock Recovery

The VSC7133 accepts differential high speed serial inputs on the RX+/RX- pins, extracts the clock and

retimes the data. Equalizers are included in the receiver to open the data eye and compensate for InterSymbol
Interference (ISI) which may be present in the incoming data. The serial bit stream should be encoded so as to
provide DC balance and limited run length by an 8B/10B encoding scheme. The Clock Recovery Unit (CRU) is
completely monolithic and requires no external components. For proper operation, the baud rate of the data
stream to be recovered should be within +200 ppm of ten times the REFCLK frequency. For example, Gigabit
Ethernet systems would use 125 MHz oscillators with a +/-100ppm accuracy resulting in +/-200 ppm between
VSC7133 pairs.

First Data Bit Transmitted

Last Data Bit Transmitted

Parallel Data Bits

8B/10B Bit Position

Comma Character

VITESSE

SEMICONDUCTOR CORPORATION

Page 3

1/17/00

741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

10-bit Transceiver for Fibre

Channel and Gigabit Ethernet

Advance Product Information

VSC7133

G52187-0 Rev. 2.4

Deserializer

The recovered serial bit stream is converted into a 10-bit parallel output character. The VSC7133 provides

complementary TTL recovered clocks, RCLK and RCLKN, which are one twentieth of the serial baud rate. The
clocks are generated by dividing down the high-speed recovered clock which is phase locked to the serial data.
The serial data is retimed, deserialized and output on R(0:9). The parallel data will be captured by the adjoin-
ing protocol logic on the rising edges of RCLK and RCLKN.

If serial input data is not present, or does not meet the required baud rate, the VSC7133 will continue to

produce a recovered clock so that downstream logic may continue to function. The RCLK/RCLKN output fre-
quency under these circumstances will differ from its expected frequency by no more than +1%.

Word Alignment

The VSC7133 provides 7-bit comma character recognition and data word alignment. Word synchronization

is enabled by asserting ENCDET HIGH. When synchronization is enabled, the receiver examines the recovered
serial data for the presence of the "Comma" character. This pattern is "0011111XXX", where the leading zero
corresponds to the first bit received. The comma sequence is not contained in any normal 8B/10B coded data
character or pair of adjacent characters. It occurs only within special characters, known as K28.1, K28.5 and
K28.7, which are defined for synchronization purposes. Improper alignment of the comma character is defined
as any of the following conditions:

1) The comma is not aligned within the 10-bit transmission character such that R(0..6) = "0011111".
2) The comma straddles the boundary between two 10-bit transmission characters.
3) The comma is properly aligned but occurs in the received character presented during the rising edge of

RCLK rather than RCLKN.

When ENCDET is HIGH and an improperly aligned comma is encountered, the recovered clock is

stretched, never slivered, so that the comma character and recovered clocks are aligned properly to R(0:9). This
results in proper character and word alignment. When the parallel data alignment changes in response to a
improperly aligned comma pattern, some data which would have been presented on the parallel output port may
be lost. Also, the first Comma pattern may be lost or corrupted. Subsequent data will be output correctly and
properly aligned. When ENCDET is LOW, the current alignment of the serial data is maintained indefinitely,
regardless of data pattern.

On encountering a comma character, COMDET is driven HIGH. The COMDET pulse is presented simul-

taneously with the comma character and has a duration equal to the data, or half of an RCLK period. The COM-
DET signal is timed such that it can be captured by the adjoining protocol logic on the rising edge of RCLKN.
Functional waveforms for synchronization are given in Figure 2 and Figure 3. Figure 2 shows the case when a
comma character is detected and no phase adjustment is necessary. It illustrates the position of the COMDET
pulse in relation to the comma character on R(0:9). Figure 3 shows the case where the K28.5 is detected, but it
is misaligned so a change in the output data alignment is required. Note that up to three characters prior to the
comma character may be corrupted by the realignment process.

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC7133

10-bit Transceiver for Fibre

Channel and Gigabit Ethernet

Page 4

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 · 805/388-3700 · FAX: 805/987-5896

1/17/00

G52187-0 Rev. 2.4

Signal Detection:

The receiver has an output, SIGDET, indicating, when HIGH, that the RX input contains a valid Fibre

Channel or Gigabit Ethernet signal. A combination of one analog and three digital checks are used to determine
if the incoming signal contains valid data. SIGDET is updated every four RCLKs. If during the current period,
all the four criteria are met, SIGDET will be HIGH during the next 4 RCLK period. If during the current period,
any of the four criteria is not met, SIGDET will be LOW during the next 4 RCLK period.

1.) Analog transition detection is performed on the input to verify that the signal swings are of adequate

amplitude. The RX+/- input buffer contains a differential voltage comparator which will go high if the differen-
tial peak-to-peak amplitude is greater than 400mV or LOW if under 200mV. If the amplitude is between 200
and 400mV, the output is indeterminate.

2.) Data on R(0:9) is monitored for all zeros (0000000000). If this pattern is encountered during the current

RCLK interval, the SIGDET output will go LOW during the next four RCLK interval.

3.) Data on R(0:9) is monitored for all ones (1111111111). If this pattern is encountered during the current

RCLK interval, the SIGDET output will go LOW during the next four RCLK interval.

4.) Data on R(0:9) is monitored for K28.5- (0011111010). Unlike previous patterns, the interval during

which a K28.5- must occur is 64K+24 10-bit characters in length. Valid Fibre Channel or Gigabit Ethernet data
will contain a K28.5- character during any period of this length. If a K28.5- is not detected during the monitor-
ing period , SIGDET will go LOW during the next period.

The behavior of SIGDET is affected by EWRAP and ENCDET as shown below.

Table 1: Signal Detect Behaviour

COMDET, RCLK, RCLKN and R(0:9) are unaltered by SIGDET.

JTAG Access Port

A JTAG Access Port is provided to assist in board-level testing. Through this port most pins can be

accessed or controlled and all TTL outputs can be tri-stated. A full description of the JTAG functions on this
device is available in "VSC7123/VSC7133 JTAG Access Port Functionality".

EWRAP

ENCDET

Transition

Detect

All Zeros/

All Ones

K28.5

Presence

Mode

Enabled

Normal

Enabled

Disabled

COMDET Disable

Enabled

Disabled

Loopback

Enabled

Disabled

Loopback

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