VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7961
3.125Gb/s PECL Limiting Amplifier with LOS Detect
G52360-0, Rev 2.0
Page 1
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Features
Applications
General Description
The VSC7961 is a single-supply limiting amplifier with Loss of Signal (LOS) detect for SONET/SDH and
Fibre Channel applications up to 3.125Gb/s. The VSC7961 provides a constant output signal swing for a wide
range of input voltages and has Positive Emitter-Coupled Logic (PECL). The VSC7959 provides the same func-
tionality as the VSC7961 with Current-Mode Logic (CML) outputs. Key features of the VSC7961 are its RMS
power detectors for programmable LOS detection, optional output squelch, adjustable output levels, excellent
jitter performance, and fast edge rates. The VSC7961 is available in die form or in a TSSOP-16 package.
Block Diagram
3.3V or 5V Power Supply
Typical Supply Current of 32mA
Positive Emitter-Coupled Logic (PECL) Outputs
Optional Output Squelch
Loss of Signal Detect
Output Offset Correction
Rise/Fall Times Faster than 100ps
Packages: TSSOP-16, Bare Die
VSC7961
100
IN+
IN-
RMS Power
Detect and
Control
Lowpass Filter
10pF
Offset Correction
8k
Output Control
8k
V
CC
V
CC
LOS
SQUELCH
LEVEL
OUT+
OUT-
LOS
CZ1
CZ2
TH
SONET/SDH at 622Mb/s, 1.244Gb/s, 2.488Gb/s,
and 3.125Gb/s
Full-Speed Fibre Channel (1.062Gb/s)
Small Form Factor (SFF) Receivers
ATM Optical Receivers
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7961
3.125Gb/s PECL Limiting Amplifier with LOS Detect
Page 2
G52360-0, Rev 2.0
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Electrical Characteristics
Table 1: DC Specifications
NOTE: (1) See Figure 4 for supply current measurement setup.
Table 2: DC Specifications
NOTES: (1) Deterministic jitter measured peak-to-peak with K28.5 pattern. (2) Random jitter measured with minimum input.
Symbol
Parameter
Min
Typ
Max
Units
Conditions
V
CC
Power Supply Voltage
3.135
5.5
V
I
CC
Power Supply Current
(1)
59
mA
V
CC
= 3.3V
62
mA
V
CC
= 5V
I
EE
Power Supply Current
(1)
31
mA
V
CC
= 3.3V
35
m
V
CC
= 5V
I
CCSQ
Power Supply Current when
Squelched
(1)
58
mA
V
CC
= 3.3V
62
mA
V
CC
= 5V
I
EESQ
Power Supply Current when
Squelched
(1)
20
mA
V
CC
= 3.3V
23
mA
V
CC
= 5V
I
SQ
Squelch Input Current
0
400
A
PSSR
Power Supply Rejection Ratio
20
dB
f < 2MHz
Symbol
Parameter
Min
Typ
Max
Units
Conditions
Data Rate
3.125
Gb/s
V
IN
Input Voltage Range
10
1200
mV
Peak-to-peak
J
D
Deterministic Jitter
25
ps
See Note 1
J
R
Random Jitter
8
ps
See Note 2, RMS
t
R,
t
F
Rise and Fall Times
55
100
ps
20% to 80%
V
N
Input Referred Noise
230
V
RMS, IN+ to IN-
R
DIFF
Differential Input Resistance
100
IN+ to IN-
f
L
Low Frequency Cutoff
2
MHz
C
Z
open
2
kHz
C
Z
= 0.1F
V
SQ
Output Signal When Squelched
20
mV
Output AC-coupled
V
OH
PECL Output High Voltage
-1025
-850
mV
-850
mV
Squelched
V
OL
PECL Output Low Voltage
-1810
-1620
mV
-1620
mV
Squelched
Z
O
Output Resistance
100
Single-ended
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7961
3.125Gb/s PECL Limiting Amplifier with LOS Detect
G52360-0, Rev 2.0
Page 3
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Table 3: Loss of Signal Specifications
Table 4: Loss of Signal Truth Table
Absolute Maximum Ratings
(1)
Power Supply Voltage (V
CC
)............................................................................................................. -0.5V to +6V
Maximum Junction Temperature Range .........................................................................................................TBD
Storage Temperature Range (T
S
)................................................................................................. -55C to +150C
NOTE: (1) CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without caus-
ing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended
periods may affect device reliability.
Recommended Operating Conditions
Positive Voltage Rail (V
CC
).................................................................................................................. 3.3V or 5V
Junction Temperature Range (T
J
)................................................................................................ -40C to +100C
Ambient Temperature Range (T
A
)................................................................................................. -40C to +85C
Symbol
Parameter
Min
Typ
Max
Units
Conditions
H
LOS
LOS Hystersis
3.1
3.3
5.5
dB
H
LOS
= 20 log (V
THD
/V
THA
)
I
LOS
LOS Assert/Deassert Time
0.22
0.25
0.28
s
V
THA
LOS Assert Threshold
8.2
mV
R
TH
= 2.5k
12.8
19.8
21.8
mV
R
TH
= 7k
57.2
mV
R
TH
= 20k
V
THD
LOS Deassert Threshold
11.4
mV
R
TH
= 2.5k
26.2
29.0
31.6
mV
R
TH
= 7k
75.2
mV
R
TH
= 20k
V
LOSH
LOS Output HIGH Voltage
3.3
V
I
LOS
= 30A
V
LOSL
LOS Output LOW Voltage
0.168
V
I
LOS
= +1.2A
SQUELCH
LOS
Output
High
Low
Off
Low
High
On
High
Low
On
Low
Low
On
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7961
3.125Gb/s PECL Limiting Amplifier with LOS Detect
Page 4
G52360-0, Rev 2.0
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Package Pin Descriptions
Figure 1: Pin Diagram
Table 5: Pin Identifications
Pin Name
Pin No.
Description
CZ1
1
Offset Correction Loop Capacitor. Place capacitor between this pin and CZ2 to alter time constant
of offset correction loop. See Detailed Description section.
CZ2
2
Offset Correction Loop Capacitor. Place capacitor between this pin and CZ1 to alter time constant
of offset correction loop. See Detailed Description section.
GND
3
Supply Ground
IN+
4
Noninverted Input Signal
IN-
5
Inverted Input Signal
GND
6
Supply Ground
NC
7
This pin may be either connected to ground of left unconnected. This pin does not effet the
performance of the device.
TH
8
Loss of Signal (LOS) Threshold. Connect a resistor from this pin to ground to set the input signal
level at which LOS outputs will be asserted. See Application Information section.
LOS
9
Inverted Loss of Signal Output. LOS is HIGH for input signals above the threshold programmed by
TH. See Detailed Description section.
LOS
10
Noninverted Loss of Signal Output. LOS is LOW for input signals above the threshold
programmed by TH. See Detailed Description section.
VCC
11
Power Supply
OUT-
12
Inverted Data Output
OUT+
13
Noninverted Data Output
VCC
14
Power Supply
SQUELCH
15
Squelch Input. Squelch is disabled if this pin is unconnected or set LOW. When SQUELCH is
HIGH, OUT+ and OUT- are forced to static levels. See Detailed Description section.
NC
16
No Connection
1
2
3
4
5
6
7
8
CZ1
CZ2
GND
IN+
IN-
GND
NC
TH
NC
SQUELCH
VCC
OUT+
OUT-
VCC
LOS
LOS
16
15
14
13
12
11
10
9
VSC7961
Top View
TSSOP-16 Package
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7961
3.125Gb/s PECL Limiting Amplifier with LOS Detect
G52360-0, Rev 2.0
Page 5
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Bare Die Descriptions
Figure 2: Pad Assignments
VSC7961
Die Size:
1597
m x 1597
m (0.06287" x 0.06287")
Pad Pitch:
180
m (0.00709")
Pad Passivation Opening:
95
m x 95
m (0.00374" x 0.00374")
Pad 16
NC
1597
m
(0.06287")
1597
m (0.06287")
Pad 2
CAZ2
Pad 3
GNDA
Pad 4
LAINP
Pad 5
LAINM
Pad 6
GNDA
Pad 7
NC
Pad 15
SQ
Pad 14
VCCA
Pad 13
LAOP
Pad 12
LAOM
Pad 11
VCCA
Pad 10
LOS
Pad 9
LOS
Pad 8
TH
Pad1
CAZ1
The back side of the die may either be left floating or connected ot ground.
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