VITESSE
SEMICONDUCTOR CORPORATION
Multi-Rate SONET/SDH
Clock and Data Recovery IC
Data Sheet
VSC8122
G52228-0, Rev 4.1
Page 1
01/05/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Features
General Description
The VSC8122 is a single-chip clock recovery IC for use in SONET OC-48, OC-24, OC-12, OC-3, or Giga-
bit Ethernet systems operating at their respective 2.48832Gb/s, 1.24416Gb/s, 622.08Mbps, 155.52Mbps, or
1.25Gbps data rates. The VSC8122 complies with SONET jitter tolerance, jitter transfer and jitter generation
specifications.
Alarm functions support typical telecom system applications. The Loss of Lock (LOL) output indicates
when the device goes out of lock, which would most often occur in the event of a loss of valid data. The NOREF
output flags when the reference input to the VSC8122 either is removed, or goes severely out of tolerance.
VSC8122 Block Diagram
Multi-Rate OC-3, OC-12, OC-24, OC-48 Clock
and Data Recovery
Supports Gigabit Ethernet
Differential Back Terminated I/O
Maintains Clock Output in the Absence of Data
Selectable Reference Clock
Loss of Lock Indicator
Exceeds SONET/SDH Requirements for Jitter
Tolerance, Jitter Transfer and Jitter Generation.
3.3V Supply Operation
1W Typical Power
64-pin , 10x10mm PQFP Packaging
DI+
DI-
Ph/Freq.
Detector
Loop
Filter
VCO
Data
Retiming
Lock
Detect
CO+
CO-
DO+
DO-
LOL
NOREF
REFCK1 +/-
REFCK0 +/-
REF_SEL[1:0]
REF_INPUTSEL
FSEL[1:0]
Divider
Divider
FILTI+/-
FILTO+/-
Data Sheet
VSC8122
Multi-Rate SONET/SDH
Clock and Data Recovery IC
VITESSE
SEMICONDUCTOR CORPORATION
Page 2
G52228-0, Rev 4.1
01/05/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Functional Description
Data Input
The data input receiver is internally terminated by a center-tapped resistor network. For differential input
AC coupling, the network is terminated to the appropriate termination voltage, V
TERM
through a blocking
capacitor, C
AC
to ground. The input requires a differential signal with a peak-to-peak voltage on both the true
and complement of a minimum of 250mV. These inputs are required to be AC-coupled to allow use with a vari-
ety of limiting amplifiers.
Figure 1: Input Termination (AC-Coupled)
High-Speed Clock and Data Outputs
The VSC8122 high-speed clock and data outputs can be DC-terminated, 50
to V
CC
as indicated in
Figure 2.
Figure 2: High-Speed Clock and Data Output DC Termination
VSC8122
Limiting Amp
0.1
F
0.1
F
DI+
DI-
Z
o
= 50
Z
o
= 50
50
50
V
TERM
C
AC
VSC8122
Z
o
= 50
Z
o
= 50
V
CC
V
CC
V
CC
50
50
100
100
CO+ / DO+
CO- / DO-
V
CC
VITESSE
SEMICONDUCTOR CORPORATION
Multi-Rate SONET/SDH
Clock and Data Recovery IC
Data Sheet
VSC8122
G52228-0, Rev 4.1
Page 3
01/05/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Outputs can also be AC terminated as shown in Figure 3. The output differential voltage and common-mode
voltage range are specified in Table 4, High-Speed Inputs and Outputs.
Figure 3: High-Speed Clock and Data Output AC Termination
Clock Recovery
The VSC8122 has a selectable input data rate. Two pins (FSEL0 and FSEL1) select the data rate to be pro-
vided to the VSC8122.
Table 1: Input Data Rate Select
The incoming data is presented both to the clock recovery circuit and the data retiming circuit. When there
is a phase error between the incoming data and the on-chip Voltage-Controlled Oscillator (VCO), the loop filter
raises or lowers the control voltage of the VCO to null the phase difference.
The lock detector monitors the frequency difference between the REFCK (optionally divided by a pres-
caler) and the recovered clock divided by 128. In the event of the loss of an input signal, or if the input is switch-
ing randomly, the VCO will move in one direction. At the time the VCO differs by more than 1MHz from the
REFCK based 2.48832GHz rate, the lock detector will assert the LOL output. LOL is designed to be asserted
from between 2.3s and 100s after the interruption of data. The VCO will continue to be frequency-locked at
approximately 1MHz off of the REFCK based 2.48832GHz rate.
When NRZ data is again presented at the data input, the phase detector will permit the VCO to lock to the
incoming data. Hysteresis is provided which delays the deassertion of LOL until approximately 160s following
the restoration of valid data.
The NOREF output will go high to indicate that there is no signal on the REFCK input, or that the REFCK
is more than approximately 25% above or below the expected value.
Input Data Rate
FSEL0
FSEL1
2.48832Gb/s or 2.5Gb/s
0
0
1.24416Gb/s or 1.25Gb/s
1
0
622.08Mb/s or 625Mb/s
0
1
155.52Mb/s or 156.25Mb/s
1
1
VSC8122
Z
o
= 50
Z
o
= 50
V
TERM
V
TERM
V
CC
V
CC
50
50
100
100
CO+ / DO+
CO- / DO-
0.1
F
0.1
F
Data Sheet
VSC8122
Multi-Rate SONET/SDH
Clock and Data Recovery IC
VITESSE
SEMICONDUCTOR CORPORATION
Page 4
G52228-0, Rev 4.1
01/05/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Two sets of reference frequencies for the VSC8122 are shown in Table 2. SONET reference clock frequen-
cies are as indicated, with Gigabit Ethernet frequencies listed in parenthesis. The two different sets of reference
clocks are needed since the reference clock for SONET and Gigabit Ethernet applications will be slightly differ-
ent. Internally, the VSC8122 requires a 19.44MHz reference (or 19.53MHz reference for Gigabit Ethernet). The
customer can select to provide either the 19.44MHz reference (or 19.53MHz reference for Gigabit Ethernet), or
the 2x, 4x or 8x of that reference at 38.88MHz (39.06MHz), 77.76MHz (78.13MHz) or 155MHz (156.25MHz).
The REF_SEL[1:0] inputs will program the internal divider as required to use the selected REFCK frequency.
Two reference clock inputs are provided, REFCK1 and REFCK0, to allow "on-the-fly switching" between
SONET and Gigabit Ethernet applications if desired. Since SONET and Gigabit Ethernet require different refer-
ence clock frequencies, the VSC8122 allows the user to toggle between the two reference clock frequencies
(REFCK1 and REFCK0) to supply the appropriate input clock. REF_INPUTSEL is used to toggle between the
two reference clock input frequencies; REF_INPUTSEL= "0" selects REFCK0 and REF_INPUTSEL= "1"
selects REFCK1. Either reference clock input (REFCK1, REFCK0) can be used for SONET or Gigabit Ethernet
reference frequencies. LVPECL levels are recommended for REFCK inputs (see Figure 4). If a reference clock
is unused, it is recommended that one of its inputs be tied to V
CC
through a 5.1k
resistor, the other one to
GND through a 5.1k
resistor.
Figure 4: REFCK Input Levels
REFCK0 /
VSC8122
VSC8122
0.1f
REFCK0 /
REFCK1
REFCK1
LVPECL Level REFCK Inputs (recommended)
NON- LVPECL Level REFCK Inputs
50
V
CC
-2
(1)
50
V
TERM
(1, 2)
NOTES: (1) For differential REFCK input signals, 100
termination between true and complement REFCK signals can be
substituted for the 50
to V
TERM
termination on each line.
(2) With the input ac-coupled, V
TERM
can be to any power supply required for the upstream device.
VITESSE
SEMICONDUCTOR CORPORATION
Multi-Rate SONET/SDH
Clock and Data Recovery IC
Data Sheet
VSC8122
G52228-0, Rev 4.1
Page 5
01/05/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Table 2: Reference Frequency
Loop Filter
The Phase-Lock Loop (PLL) on the VSC8122 employs two external capacitors. The PLL design is fully
differential, therefore the loop filter must also be fully differential. One capacitor should be connected between
FILTAO and FILTAI, with the other connected between FILTAON and FILTAIN. Recommended capacitors are
low-inductance 1.0
F (0603 or 0805) ceramic SMT X7R devices, 6.3 WVDC or greater, with tolerance of 10%
or better.
AC Characteristics
(Over recommended operating conditions)
Table 3: AC Characteristics
Reference Frequency
REF_SEL0
REF_SEL1
19.44MHz (19.53MHz)
0
0
38.88MHz (39.06MHz)
1
0
77.76MHz (78.13MHz)
0
1
155.52MHz (156.25MHz)
1
1
Parameters
Description
Min
Typ
Max
Units
Conditions
t
pd
Center of output data eye from
rising edge of CO+
-75
--
+75
ps
t
r
,t
f
DO
rise and fall times
--
--
150
ps
20% to 80% into 50
load.
t
r
,t
f
CO
rise and fall times
--
--
135
ps
20% to 80% into 50
load.
Jitter
gen
Jitter Generation (12kHz-
20MHz)
--
--
3.6
ps - rms
Measured at the HS data output for
jitter in the 12kHz - 20MHz band.
Assume 1.2ps rms input data jitter.
Jitter
tol
Jitter Tolerance
--
--
--
--
Exceeds SONET/SDH mask
LBW
Loop Bandwidth
--
--
2.0
MHz
-3dB point of jitter transfer curve
Jitter
peak
Jitter Peaking
--
--
0.1
dB
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