VITESSE
SEMICONDUCTOR CORPORATION
Page 1
9/14/98
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8162
2.488 Gbit/sec SONET/SDH
1:16 Demux with Clock Recovery
G52209-0, Rev. 2.0
Features
General Description
The VSC8162 combines a clock recovery unit (CRU) with a 1:16 demultiplexer on a single chip to directly
generate 16-bit wide data from an incoming 2.488Gb/s NRZ data stream. An on-chip Phase Locked Loop (PLL)
generates a 2.488GHz clock which remains phase locked to the incoming data. The incoming data is retimed
and demultiplexed to a 16-bit word. A Loss of Lock (LOL) signal indicates gross conditions where incoming
data no longer has sufficient transitions to keep the CRU in lock.
VSC8162 Functional Block DIagram
2.488Gb/s 1:16 Demux with Integrated Clock and
Data Recovery
Recovered Clock and Data Available
Monolithic Phase Locked Loop
Digitally Adjustable Serial Data Sampling Point
Differential Low Speed Outputs
Differential/Single-ended Reference Clock
Loss of Lock Detection
Meets SONET OC-48 and SDH STM-16 Jitter
Tolerance Requirements
RTDO+
RTDO
D0+
D0
D15+
D15
PARITY+
PARITY
CLK16+
CLK16
CLKO+
CLKO
DI+
DI
REFCK+
REFCK
PADJ[4:0]
DINVERT
LOL
NOREF
Clock
Recovery
Data
Retime
Divide
by 16
Output Register
5
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8162
2.488 Gbit/sec SONET/SDH
1:16 Demux with Clock Recovery
Page 2
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
9/14/98
G52209-0, Rev. 2.0
Functional Description
Clock Recovery:
The clock recovery unit (CRU) consists of a phase detector, voltage controlled oscillator (VCO), loop filter
and frequency control unit (FCU). The components of the CRU are fully integrated on the VSC8162. A
19.44MHz reference clock (REFCLK) is required for proper operation of the Clock Recovery Unit (CRU). Jit-
ter tolerance of the CRU is well above the SONET and SDH jitter tolerance masks. In addition, the recovered
high speed clock is output on the CLKO pins.
Incoming data is presented to both the clock recovery circuit and the data retiming circuit. When the CRU is
in lock mode, a phase detector circuit is effective. When there is a phase error between the incoming data and
the on-chip VCO, the phase detector output raises or lowers the voltage on the loop filter to null the phase dif-
ference.
The frequency control unit (FCU) monitors the frequency difference between the reference clock, REFCK,
and the recovered clock. At the time that the VCO frequency,
f
VCO
, and the 128x REFCK frequency,
128
x
f
REF
,
differ by less than 1 MHz, the FCU only passively monitors the frequency difference continuously without
sending any corrections to the loop filter. In the event of the loss of an input signal, or if the input is switching
randomly, the VCO will drift in one direction. At the time that
f
VCO
and
128
x
f
REF
differ by more than 1 MHz,
the FCU will maintain the VCO frequency to be at approximately 1MHz off the frequency of
128
x
f
REF
, and the
lock detector will assert the LOL output. LOL is designed to be asserted from between 2.3us and 100us after the
interruption of data.
When NRZ data is again presented at the data input, the phase detector will permit the VCO to lock to the
incoming data. Hysteresis is provided which delays the deassertion of LOL until approximately 160us follow-
ing the restoration of valid data.
The NOREF output will go high to indicate that there is no signal on the REFCK input, or that the REFCK
is more than approximately 25% above or below the expected value.
Retiming:
The retiming decision circuit functions as a D Flip Flop. The recovered clock nominally clocks the decision
circuit in the center of the data eye. Internally, the recovered clock is duplicated to create 32 copies, with a phase
difference between each of 1/32 of a unit interval. The PADJ[4:0] inputs select which of the 32 phases are to be
used to retime the data. Certain lightwave systems employing optical amplifiers suffer from noise in the leading
edge of the data eye. Therefore these systems may achieve their lowest Bit Error Rate (BER) by delaying the
retiming point until later in the eye. The PADJ inputs can be strapped to generate a fixed delay or the customer
can develop a dynamic circuit which can select the optimum retiming point during a training sequence. The
retimed high speed data can be monitored using the RTDO pins.
Figure 1 and Table 1 indicate how the PADJ pins adjust the sampling point in the data eye. The step size of
each unit interval is approximately 12.5ps. The values in Table 1 are not exact and should be used only as an
approximation of the expected delay. Due to environmental variations, the actual measured value at any point
could vary by as much as +/- 1 step size. It should be noted that PADJ[4:0] = `00000' always corresponds to the
sampling center point and that the delay between unit intervals increases monotonically.
VITESSE
SEMICONDUCTOR CORPORATION
Page 3
9/14/98
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8162
2.488 Gbit/sec SONET/SDH
1:16 Demux with Clock Recovery
G52209-0, Rev. 2.0
PADJ are ECL compatible inputs (see Table 6). If the pins are left floating, the inputs will default to the
logic low state. In order to set to a logic high level, the inputs can be tied directly to V
CC
without the need for a
resistor.
Table 1: Retiming Phase Adjust Settings
PADJ4
PADJ3
PADJ2
PADJ1
PADJ0
Degrees
From Center
PS From
Center
0
0
0
0
0
0.00
0.0
0
0
0
0
1
11.25
12.6
0
0
0
1
0
22.50
25.1
0
0
0
1
1
33.75
37.7
0
0
1
0
0
45.00
50.2
0
0
1
0
1
56.25
62.8
0
0
1
1
0
67.50
75.4
0
0
1
1
1
78.75
87.9
0
1
0
0
0
90.00
100.5
0
1
0
0
1
101.25
113.0
0
1
0
1
0
112.50
125.6
0
1
0
1
1
123.75
138.2
0
1
1
0
0
135.00
150.7
0
1
1
0
1
146.25
163.3
0
1
1
1
0
157.50
175.8
0
1
1
1
1
168.75
188.4
1
0
0
0
0
180.00
201.0
1
0
0
0
1
-168.75
-188.4
1
0
0
1
0
-157.50
-175.8
1
0
0
1
1
-146.25
-163.3
1
0
1
0
0
-135.00
-150.7
1
0
1
0
1
-123.75
-138.2
1
0
1
1
0
-112.50
-125.6
1
0
1
1
1
-101.25
-113.0
1
1
0
0
0
-90.00
-100.5
1
1
0
0
1
-78.75
-87.9
1
1
0
1
0
-67.50
-75.4
1
1
0
1
1
-56.25
-62.8
1
1
1
0
0
-45.00
-50.2
1
1
1
0
1
-33.75
-37.7
1
1
1
1
0
-22.50
-25.1
1
1
1
1
1
-11.25
-12.6
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8162
2.488 Gbit/sec SONET/SDH
1:16 Demux with Clock Recovery
Page 4
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
9/14/98
G52209-0, Rev. 2.0
Figure 1: Retiming Offset
1:16 Demultiplexer
The demultiplexer inside of the VSC8162 consists of a 1:16 demultiplexer and timing circuitry which gen-
erates a divide-by-16 clock from the high speed clock input. The demultiplexer accepts a serial data stream
input (DI+/DI-) at 2.488 Gb/s and deserializes it into 16 parallel differential outputs (D0..D15). The timing
parameters of the parallel data outputs (D0..D15) are specified with respect to the falling edge of CLK16, so
that CLK16 can be used to clock the destination of D0..D15.
The parity output of the demultiplexer is the XOR of all 16 parallel outputs. The DINVERT input is an ECL
input (see Table 6) which can be used to invert the sense of the data through the demultiplexer. If DINVERT is
left floating, it defaults to the low state, which is the state that corresponds to normal operation (no data inver-
sion).
FILTI, FILTO Pins
The FILTI and FILTO pins are used to provide additional capacitance to the loop filter of the VCO. To opti-
mize the VCO's performance, it is recommended that 0.1
F, size 0805 capacitors are connected between the
FILTI+ and FILTI- pins, as well as the FILTO+ and FILTO- pins.
Supplies
The VSC8161 is designed to operate with V
EE
= -5.2V, V
TT
= -2.0V and V
CC
= GND (0.0V). However,
the part can be operated in an all positive supply environment, or a mixed positive and negative supply environ-
ment.
To operate in an all positive supply environment, each of the supply voltages must be shifted up by 5.2V
such that V
EE
will now be GND, V
TT
= +3.2V and V
CC
= +5.2V. To operate in a mixed positive and negative
supply environment, each of the supply voltages must be shifted up by 2.0V such that V
TT
will now be GND,
V
EE
= -3.2V and V
CC
= +2.0V
.
Bear in mind that termination voltages must be adjusted to reflect any shift in supply voltages.
Sampling point at the
center of the eye
Sampling point
delayed ~50ps from
the center of the eye
PH_ADJ[4:0] = 00100
DI
PH_ADJ[4:0] = 00000
VITESSE
SEMICONDUCTOR CORPORATION
Page 5
9/14/98
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8162
2.488 Gbit/sec SONET/SDH
1:16 Demux with Clock Recovery
G52209-0, Rev. 2.0
Interface Recommendations
REFCK+, REFCK Inputs
Internal biasing will position the reference voltage of approximately -1.32V on both the true and comple-
ment inputs. This input can either be DC coupled or AC coupled; it can also be driven single-ended or differen-
tially. Figure 2 shows the configuration for single-ended, AC-coupling operation. In the case of direct coupling
and single-ended input, it is recommended that a stable V
REF
for ECL levels be used for the complementary
input.
Figure 2: Single-ended AC Coupling for REFCK+, REFCK Inputs
V
TT
REFCK+
REFCK
V
CC
= GND
V
TT
= -2V
-1.32V
-1.32V
R
| |
= 1k
(Approx.)
C
IN
C
SE
V
TT
Chip Boundary
C
IN
TYP = 0.1
F
C
SE
TYP = 0.1
F for single ended applications.
Z
O
R
T
= Z
O
selected for REFCLK = 19.44 MHz)
(Capacitor values are
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