VITESSE
SEMICONDUCTOR CORPORATION
Page 1
11/9/99
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC8166
2.488 Gbit/sec
1:16 SONET/SDH Demux with Clock Recovery
G52252-0, Rev. 3.0
Features
General Description
The VSC8166 demultiplexes a 2.488Gbp/s LVPECL serial input datastream (DI+) to 16-bit wide, LVPECL
155Mb/s parallel data outputs (D0:D15+) for SONET/SDH applications. It has an integrated clock and data
recovery unit with an on-chip PLL that internally generates a 2.488GHz clock in phase with the incoming data.
Internal divider circuits are used to take the high-speed clock and generate 155.52MHz (CLK16O+) and
77.76MHz (CLK32O+) LVPECL external output clocks. The incoming data is retimed and demultiplexed to a
16-bit word which is clocked out of the demultiplexer by the 155.52MHz output clock.
Alarm functions support typical telecom system applications. A TTL Loss Of Lock (LOL) indicator can be
externally enabled (LOLEN) to detect when the device goes out of lock, which would most often occur in the
event of a loss of valid data. A TTL No-Reference (NOREF) output indicator flags when the LVPECL Clock
Reference (REFCLK) input to the VSC8166 either is removed, or goes severely out of tolerance. For Loss Of
Signal (LOS) conditions from an Optics Module, the VSC8166 provides a polarity (POL) input to accommo-
date any polarity differences.
Only a single 3.3V power supply is required for device operation and the device is packaged in a thermally
enhanced 128 Pin 14x20x2 mm PQFP Package.
VSC8166 Block DIagram
2.488Gb/s 1:16 Demultiplexer
Fully Integrated Clock and Data Recovery
Single 3.3V Supply Operation
Differential LVPECL Low Speed Interface
Maintains Clock Output in the Absence of
Data
Loss of Lock, Loss of Signal Indicators
128 Pin 14x20x2 mm Enhanced PQFP Pkg.
2.3W Max Power Dissipation
Out
pu
t
Regi
s
t
e
r
1
:
16 DM
UX
Clock
Recovery
Data
Divide
by 16
Divide
by 2
D0+
D0-
D15+
D15-
CLK16O+
CLK16O-
CLK32O+
CLK32O-
DI+
DI-
REFCLK+
REFCLK-
Re-time
NOREF
LOS
LOLEN
LOL
POL
1
0
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC8166
2.488 Gbit/sec
1:16 SONET/SDH Demux with Clock Recovery
Page 2
VITESSE
SEMICONDUCTOR CORPORATION
G52252-0, Rev 3.0
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
11/9/99
Functional Description
Clock Recovery:
The incoming SONET/SDH data stream is fed both to a re-timing latch and to the integrated clock recovery
unit (CRU). The CRU exceeds the SONET/SDH jitter tolerance map. A 77.76MHz reference clock (REF-
CLK+) is required for CRU operation. Off-chip termination of this input is required. For AC coupling, a bias
voltage suitable for AC coupling needs to be provided, see Figure 1 for biasing scheme. The 77.76MHz refer-
ence is used to permit the CLK16O+ to remain locked to this external reference clock in the event of data loss.
Figure 1: AC Termination of LVPECL REFCLK Input
The VSC8166 has a TTL input LOS to force the part into a Loss of Signal state. Most optics have a TTL
output usually called "SD" (Signal Detect), based on the optical power of the incoming light stream. Depending
on the optics manufacturer, this signal is either active high or low. To accommodate polarity differences, the
internal Loss of Signal is generated when the POL and LOS inputs are of opposite states. Once active, all zeroes
"0" will be propagated downstream using the transmit clock until the optical signal is regained and LOS and
POL are in the same logic state. When LOS and POL are opposite logic states, an internal LOS is asserted and
all output data D(0:15)+ will go to zero on the next rising edge of CLK16O+.
If LOLEN is low, and the serial input data consists of 3.3us or more of continuous zeros, LOL will go high
and remain high for 100us following the restoration of valid data. If LOLEN is high, loss of data lock "OR"
3.3us of zeros will cause LOL to go high and remain high for 100us after both the return of non-zero data, and
phase locking of the Serial data and clock are obtained.
NOREF will go high asynchronously when REFCLK is lost, or when REFCLK is not locked to the internal
2.488GHZ clock. It will remain high until the condition is corrected.
V
CC
= 3.3V
V
EE
= 0V
C
IN
Chip Boundary
Z
O
C
IN
TYP = 100 nF
for AC operation.
R2
R1
V
CC
V
EE
C
IN
Z
O
R2
R1
V
CC
V
EE
Split-end equivalent termination is Zo to V
Term
R1 = 125
, R2 = 83
, Zo=50
, V
Term
= V
CC
-2V
V
CC
R2 + V
EE
R1
R1+R2
= V
Bias
R1||R2 = Z
o
VITESSE
SEMICONDUCTOR CORPORATION
Page 3
11/9/99
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC8166
2.488 Gbit/sec
1:16 SONET/SDH Demux with Clock Recovery
G52252-0, Rev. 3.0
Low Speed Interface
The demultiplexed serial stream is made available by a 16 bit differential LVPECL interface D(15:0)+ with
accompanying differential LVPECL divide by 16 clock CLK16O
and divide by 32 clock CLK32O
. The low
speed LVPECL output drivers are designed to drive a 50
transmission line. The transmission line can be DC
terminated with a split end termination scheme, see Figure 2, or DC terminated by 50
to V
CC
-2V on each line,
see Figure 3. At any time, the equivalent split-end termination technique can be substituted for the traditional
50
to V
CC
-2V on each line. AC coupling can be achieved by a number of methods. Figure 4 illustrates an AC
coupling method for the occasion when the downstream device provides the bias point for AC coupling. If the
downstream device were to have internal termination, the line to line 100
resistor may not be necessary. The
divide by 32 output can be used to provide a reference clock for the clock multiplication unit on the VSC8163.
Figure 2: Split-end DC Termination of Low Speed LVPECL CLK16O, CLK32O, D[15:0] Outputs
Figure 3: Traditional DC Termination of Low Speed LVPECL CLK16O, CLK32O, D[15:0] Outputs
VSC8166
Z
o
Z
o
R2
R2
R1
R1
VEE
VCC
downstream
Split-end equivalent termination is Zo to V
Term
R1 = 125
R2 = 83
, Zo=50
, V
Term
= V
CC
-2V
V
CC
R2 + V
EE
R1
R1+R2
= V
Term
R1||R2 = Z
o
V
CC
-2V
R1 =50
VSC8166
Z
o
V
CC
-2V
R1 =50
downstream
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC8166
2.488 Gbit/sec
1:16 SONET/SDH Demux with Clock Recovery
Page 4
VITESSE
SEMICONDUCTOR CORPORATION
G52252-0, Rev 3.0
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
11/9/99
Figure 4: AC Termination of Low Speed LVPECL CLK16O, CLK32O, D[15:0] Outputs
High Speed Interface
The incoming 2.488Gb/s data is received by high speed inputs DI+. The data inputs are internally termi-
nated by a center-tapped resistor network. For differential input DC coupling, the network is terminated to the
appropriate termination voltage V
TERM
(pins HSDREF) providing a 50
to V
TERM
termination for both true
and complement inputs. For differential input AC coupling, the network is terminated to V
TERM
via a blocking
capacitor.
In most situations these inputs will have high transition density and little DC offset. However, in cases
where this does not hold, direct DC connection is possible. Serial data inputs have the circuit topology shown in
Figure 5. The reference voltage is created by a resistor divider as shown. If the input signal is driven differen-
tially and DC-coupled to the part, the mid-point of the input signal swing should be centered about this refer-
ence voltage and not exceed the maximum allowable amplitude (
V
CMI
,
V
IHS
)
. For single-ended, DC-coupling
operations, it is recommended that the user provides an external reference voltage which has better temperature
and power supply noise rejection than the on-chip resistor divider. The external reference should have a nominal
value equivalent to the common mode switch point of the DC coupled signal, and can be connected to either
side of the differential gate.
VSC8166
0.1uF
50
50
Z
o
Z
o
0.1uF
V
CC
-2V
downstream
bias point
generated
internally
VITESSE
SEMICONDUCTOR CORPORATION
Page 5
11/9/99
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC8166
2.488 Gbit/sec
1:16 SONET/SDH Demux with Clock Recovery
G52252-0, Rev. 3.0
Figure 5: High Speed Serial Data Inputs
Supplies
This device is specified as a LVPECL device with a single positive 3.3V supply. Should the user desire to
use the device in a ECL environment with a negative 3.3V supply, then VCC will be ground and VEE will be -
3.3V.
Decoupling of the power supplies is a critical element in maintaining the proper operation of the part. It is
recommended that the V
CC
power supply be decoupled using a 0.1
F and 0.01
F capacitor placed in parallel on
each V
CC
power supply pin as close to the package as possible. If room permits, a 0.001
F capacitor should
also be placed in parallel with the 0.1
F and 0.01
F capacitors mentioned above. Recommended capacitors are
low inductance ceramic SMT X7R devices. For the 0.1
F capacitor, a 0603 package should be used. The
0.01
F and 0.001
F capacitors can be either 0603 or 0403 packages.
For low frequency decoupling, 47
F tantalum low inductance SMT caps should be sprinkled over the
board's main +3.3V power supply and placed close to the C-L-C pi filter.
If the device is being used in an ECL environment with a -3.3V supply, then all references to decoupling
V
CC
must be changed to V
EE
, and all references to decoupling 3.3V must be changed to -3.3V.
V
CC
= 3.3V
V
EE
= 0V
C
IN
Chip Boundary
C
IN
TYP = 100 pF
C
AC
TYP = 100pF
Z
O
V
Term
C
AC
50
50
C
IN
Z
O
PDF 
ZIP